# 1 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
# 1 "<built-in>" 1
# 1 "<built-in>" 3
# 401 "<built-in>" 3
# 1 "<command line>" 1
# 1 "<built-in>" 2
# 1 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c" 2
# 27 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 1
# 84 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h"
# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_crm.h" 1
# 37 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_crm.h"
# 1 "../core/AT32F435CGU7/libraries/cmsis/cm4/device_support\\at32f435_437.h" 1
# 131 "../core/AT32F435CGU7/libraries/cmsis/cm4/device_support\\at32f435_437.h"
typedef enum IRQn
{

    Reset_IRQn = -15,
    NonMaskableInt_IRQn = -14,
    HardFault_IRQn = -13,
    MemoryManagement_IRQn = -12,
    BusFault_IRQn = -11,
    UsageFault_IRQn = -10,
    SVCall_IRQn = -5,
    DebugMonitor_IRQn = -4,
    PendSV_IRQn = -2,
    SysTick_IRQn = -1,


    WWDT_IRQn = 0,
    PVM_IRQn = 1,
    TAMP_STAMP_IRQn = 2,
    ERTC_WKUP_IRQn = 3,
    FLASH_IRQn = 4,
    CRM_IRQn = 5,
    EXINT0_IRQn = 6,
    EXINT1_IRQn = 7,
    EXINT2_IRQn = 8,
    EXINT3_IRQn = 9,
    EXINT4_IRQn = 10,
    EDMA_Stream1_IRQn = 11,
    EDMA_Stream2_IRQn = 12,
    EDMA_Stream3_IRQn = 13,
    EDMA_Stream4_IRQn = 14,
    EDMA_Stream5_IRQn = 15,
    EDMA_Stream6_IRQn = 16,
    EDMA_Stream7_IRQn = 17,


    ADC1_2_3_IRQn = 18,
    CAN1_TX_IRQn = 19,
    CAN1_RX0_IRQn = 20,
    CAN1_RX1_IRQn = 21,
    CAN1_SE_IRQn = 22,
    EXINT9_5_IRQn = 23,
    TMR1_BRK_TMR9_IRQn = 24,
    TMR1_OVF_TMR10_IRQn = 25,
    TMR1_TRG_HALL_TMR11_IRQn = 26,
    TMR1_CH_IRQn = 27,
    TMR2_GLOBAL_IRQn = 28,
    TMR3_GLOBAL_IRQn = 29,
    TMR4_GLOBAL_IRQn = 30,
    I2C1_EVT_IRQn = 31,
    I2C1_ERR_IRQn = 32,
    I2C2_EVT_IRQn = 33,
    I2C2_ERR_IRQn = 34,
    SPI1_IRQn = 35,
    SPI2_I2S2EXT_IRQn = 36,
    USART1_IRQn = 37,
    USART2_IRQn = 38,
    USART3_IRQn = 39,
    EXINT15_10_IRQn = 40,
    ERTCAlarm_IRQn = 41,
    OTGFS1_WKUP_IRQn = 42,
    TMR8_BRK_TMR12_IRQn = 43,
    TMR8_OVF_TMR13_IRQn = 44,
    TMR8_TRG_HALL_TMR14_IRQn = 45,
    TMR8_CH_IRQn = 46,
    EDMA_Stream8_IRQn = 47,
    XMC_IRQn = 48,
    SDIO1_IRQn = 49,
    TMR5_GLOBAL_IRQn = 50,
    SPI3_I2S3EXT_IRQn = 51,
    UART4_IRQn = 52,
    UART5_IRQn = 53,
    TMR6_DAC_GLOBAL_IRQn = 54,
    TMR7_GLOBAL_IRQn = 55,
    DMA1_Channel1_IRQn = 56,
    DMA1_Channel2_IRQn = 57,
    DMA1_Channel3_IRQn = 58,
    DMA1_Channel4_IRQn = 59,
    DMA1_Channel5_IRQn = 60,
    CAN2_TX_IRQn = 63,
    CAN2_RX0_IRQn = 64,
    CAN2_RX1_IRQn = 65,
    CAN2_SE_IRQn = 66,
    OTGFS1_IRQn = 67,
    DMA1_Channel6_IRQn = 68,
    DMA1_Channel7_IRQn = 69,
    USART6_IRQn = 71,
    I2C3_EVT_IRQn = 72,
    I2C3_ERR_IRQn = 73,
    OTGFS2_WKUP_IRQn = 76,
    OTGFS2_IRQn = 77,
    DVP_IRQn = 78,
    FPU_IRQn = 81,
    UART7_IRQn = 82,
    UART8_IRQn = 83,
    SPI4_IRQn = 84,
    QSPI2_IRQn = 91,
    QSPI1_IRQn = 92,
    DMAMUX_IRQn = 94,
    SDIO2_IRQn = 102,
    ACC_IRQn = 103,
    TMR20_BRK_IRQn = 104,
    TMR20_OVF_IRQn = 105,
    TMR20_TRG_HALL_IRQn = 106,
    TMR20_CH_IRQn = 107,
    DMA2_Channel1_IRQn = 108,
    DMA2_Channel2_IRQn = 109,
    DMA2_Channel3_IRQn = 110,
    DMA2_Channel4_IRQn = 111,
    DMA2_Channel5_IRQn = 112,
    DMA2_Channel6_IRQn = 113,
    DMA2_Channel7_IRQn = 114,
# 325 "../core/AT32F435CGU7/libraries/cmsis/cm4/device_support\\at32f435_437.h"
} IRQn_Type;





# 1 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 1
# 29 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3





# 1 "C:\\Keil_v5\\ARM\\ARMCLANG\\bin\\..\\include\\stdint.h" 1 3
# 56 "C:\\Keil_v5\\ARM\\ARMCLANG\\bin\\..\\include\\stdint.h" 3
typedef signed char int8_t;
typedef signed short int int16_t;
typedef signed int int32_t;
typedef signed long long int int64_t;


typedef unsigned char uint8_t;
typedef unsigned short int uint16_t;
typedef unsigned int uint32_t;
typedef unsigned long long int uint64_t;





typedef signed char int_least8_t;
typedef signed short int int_least16_t;
typedef signed int int_least32_t;
typedef signed long long int int_least64_t;


typedef unsigned char uint_least8_t;
typedef unsigned short int uint_least16_t;
typedef unsigned int uint_least32_t;
typedef unsigned long long int uint_least64_t;




typedef signed int int_fast8_t;
typedef signed int int_fast16_t;
typedef signed int int_fast32_t;
typedef signed long long int int_fast64_t;


typedef unsigned int uint_fast8_t;
typedef unsigned int uint_fast16_t;
typedef unsigned int uint_fast32_t;
typedef unsigned long long int uint_fast64_t;






typedef signed int intptr_t;
typedef unsigned int uintptr_t;



typedef signed long long intmax_t;
typedef unsigned long long uintmax_t;
# 35 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 2 3
# 63 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
# 1 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_version.h" 1 3
# 29 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_version.h" 3
# 64 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 2 3
# 162 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
# 1 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_compiler.h" 1 3
# 47 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_compiler.h" 3
# 1 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 1 3
# 31 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3


# 1 "C:\\Keil_v5\\ARM\\ARMCLANG\\bin\\..\\include\\arm_compat.h" 1 3






# 1 "C:\\Keil_v5\\ARM\\ARMCLANG\\bin\\..\\include\\arm_acle.h" 1 3
# 45 "C:\\Keil_v5\\ARM\\ARMCLANG\\bin\\..\\include\\arm_acle.h" 3
static __inline__ void __attribute__((__always_inline__, __nodebug__)) __wfi(void) {
  __builtin_arm_wfi();
}



static __inline__ void __attribute__((__always_inline__, __nodebug__)) __wfe(void) {
  __builtin_arm_wfe();
}



static __inline__ void __attribute__((__always_inline__, __nodebug__)) __sev(void) {
  __builtin_arm_sev();
}



static __inline__ void __attribute__((__always_inline__, __nodebug__)) __sevl(void) {
  __builtin_arm_sevl();
}



static __inline__ void __attribute__((__always_inline__, __nodebug__)) __yield(void) {
  __builtin_arm_yield();
}







static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
__swp(uint32_t __x, volatile uint32_t *__p) {
  uint32_t v;
  do
    v = __builtin_arm_ldrex(__p);
  while (__builtin_arm_strex(__x, __p));
  return v;
}
# 113 "C:\\Keil_v5\\ARM\\ARMCLANG\\bin\\..\\include\\arm_acle.h" 3
static __inline__ void __attribute__((__always_inline__, __nodebug__)) __nop(void) {
  __builtin_arm_nop();
}





static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
__ror(uint32_t __x, uint32_t __y) {
  __y %= 32;
  if (__y == 0)
    return __x;
  return (__x >> __y) | (__x << (32 - __y));
}

static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
__rorll(uint64_t __x, uint32_t __y) {
  __y %= 64;
  if (__y == 0)
    return __x;
  return (__x >> __y) | (__x << (64 - __y));
}

static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
__rorl(unsigned long __x, uint32_t __y) {

  return __ror(__x, __y);



}



static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__clz(uint32_t __t) {
  return __builtin_arm_clz(__t);
}

static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__clzl(unsigned long __t) {

  return __builtin_arm_clz(__t);



}

static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__clzll(uint64_t __t) {
  return __builtin_arm_clz64(__t);
}


static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__cls(uint32_t __t) {
  return __builtin_arm_cls(__t);
}

static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__clsl(unsigned long __t) {

  return __builtin_arm_cls(__t);



}

static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__clsll(uint64_t __t) {
  return __builtin_arm_cls64(__t);
}


static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
__rev(uint32_t __t) {
  return __builtin_bswap32(__t);
}

static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
__revl(unsigned long __t) {

  return __builtin_bswap32(__t);



}

static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
__revll(uint64_t __t) {
  return __builtin_bswap64(__t);
}


static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
__rev16(uint32_t __t) {
  return __ror(__rev(__t), 16);
}

static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
__rev16ll(uint64_t __t) {
  return (((uint64_t)__rev16(__t >> 32)) << 32) | (uint64_t)__rev16((uint32_t)__t);
}

static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
__rev16l(unsigned long __t) {

    return __rev16(__t);



}


static __inline__ int16_t __attribute__((__always_inline__, __nodebug__))
__revsh(int16_t __t) {
  return (int16_t)__builtin_bswap16((uint16_t)__t);
}


static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
__rbit(uint32_t __t) {
  return __builtin_arm_rbit(__t);
}

static __inline__ uint64_t __attribute__((__always_inline__, __nodebug__))
__rbitll(uint64_t __t) {

  return (((uint64_t)__builtin_arm_rbit(__t)) << 32) |
         __builtin_arm_rbit(__t >> 32);



}

static __inline__ unsigned long __attribute__((__always_inline__, __nodebug__))
__rbitl(unsigned long __t) {

  return __rbit(__t);



}



static __inline__ int32_t __attribute__((__always_inline__,__nodebug__))
__smulbb(int32_t __a, int32_t __b) {
  return __builtin_arm_smulbb(__a, __b);
}
static __inline__ int32_t __attribute__((__always_inline__,__nodebug__))
__smulbt(int32_t __a, int32_t __b) {
  return __builtin_arm_smulbt(__a, __b);
}
static __inline__ int32_t __attribute__((__always_inline__,__nodebug__))
__smultb(int32_t __a, int32_t __b) {
  return __builtin_arm_smultb(__a, __b);
}
static __inline__ int32_t __attribute__((__always_inline__,__nodebug__))
__smultt(int32_t __a, int32_t __b) {
  return __builtin_arm_smultt(__a, __b);
}
static __inline__ int32_t __attribute__((__always_inline__,__nodebug__))
__smulwb(int32_t __a, int32_t __b) {
  return __builtin_arm_smulwb(__a, __b);
}
static __inline__ int32_t __attribute__((__always_inline__,__nodebug__))
__smulwt(int32_t __a, int32_t __b) {
  return __builtin_arm_smulwt(__a, __b);
}
# 300 "C:\\Keil_v5\\ARM\\ARMCLANG\\bin\\..\\include\\arm_acle.h" 3
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
__qadd(int32_t __t, int32_t __v) {
  return __builtin_arm_qadd(__t, __v);
}

static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
__qsub(int32_t __t, int32_t __v) {
  return __builtin_arm_qsub(__t, __v);
}

static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
__qdbl(int32_t __t) {
  return __builtin_arm_qadd(__t, __t);
}




static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
__smlabb(int32_t __a, int32_t __b, int32_t __c) {
  return __builtin_arm_smlabb(__a, __b, __c);
}
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
__smlabt(int32_t __a, int32_t __b, int32_t __c) {
  return __builtin_arm_smlabt(__a, __b, __c);
}
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
__smlatb(int32_t __a, int32_t __b, int32_t __c) {
  return __builtin_arm_smlatb(__a, __b, __c);
}
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
__smlatt(int32_t __a, int32_t __b, int32_t __c) {
  return __builtin_arm_smlatt(__a, __b, __c);
}
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
__smlawb(int32_t __a, int32_t __b, int32_t __c) {
  return __builtin_arm_smlawb(__a, __b, __c);
}
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
__smlawt(int32_t __a, int32_t __b, int32_t __c) {
  return __builtin_arm_smlawt(__a, __b, __c);
}
# 353 "C:\\Keil_v5\\ARM\\ARMCLANG\\bin\\..\\include\\arm_acle.h" 3
typedef int32_t int8x4_t;
typedef int32_t int16x2_t;
typedef uint32_t uint8x4_t;
typedef uint32_t uint16x2_t;

static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
__sxtab16(int16x2_t __a, int8x4_t __b) {
  return __builtin_arm_sxtab16(__a, __b);
}
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
__sxtb16(int8x4_t __a) {
  return __builtin_arm_sxtb16(__a);
}
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
__uxtab16(int16x2_t __a, int8x4_t __b) {
  return __builtin_arm_uxtab16(__a, __b);
}
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
__uxtb16(int8x4_t __a) {
  return __builtin_arm_uxtb16(__a);
}




static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__))
__sel(uint8x4_t __a, uint8x4_t __b) {
  return __builtin_arm_sel(__a, __b);
}




static __inline__ int8x4_t __attribute__((__always_inline__, __nodebug__))
__qadd8(int8x4_t __a, int8x4_t __b) {
  return __builtin_arm_qadd8(__a, __b);
}
static __inline__ int8x4_t __attribute__((__always_inline__, __nodebug__))
__qsub8(int8x4_t __a, int8x4_t __b) {
  return __builtin_arm_qsub8(__a, __b);
}
static __inline__ int8x4_t __attribute__((__always_inline__, __nodebug__))
__sadd8(int8x4_t __a, int8x4_t __b) {
  return __builtin_arm_sadd8(__a, __b);
}
static __inline__ int8x4_t __attribute__((__always_inline__, __nodebug__))
__shadd8(int8x4_t __a, int8x4_t __b) {
  return __builtin_arm_shadd8(__a, __b);
}
static __inline__ int8x4_t __attribute__((__always_inline__, __nodebug__))
__shsub8(int8x4_t __a, int8x4_t __b) {
  return __builtin_arm_shsub8(__a, __b);
}
static __inline__ int8x4_t __attribute__((__always_inline__, __nodebug__))
__ssub8(int8x4_t __a, int8x4_t __b) {
  return __builtin_arm_ssub8(__a, __b);
}
static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__))
__uadd8(uint8x4_t __a, uint8x4_t __b) {
  return __builtin_arm_uadd8(__a, __b);
}
static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__))
__uhadd8(uint8x4_t __a, uint8x4_t __b) {
  return __builtin_arm_uhadd8(__a, __b);
}
static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__))
__uhsub8(uint8x4_t __a, uint8x4_t __b) {
  return __builtin_arm_uhsub8(__a, __b);
}
static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__))
__uqadd8(uint8x4_t __a, uint8x4_t __b) {
  return __builtin_arm_uqadd8(__a, __b);
}
static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__))
__uqsub8(uint8x4_t __a, uint8x4_t __b) {
  return __builtin_arm_uqsub8(__a, __b);
}
static __inline__ uint8x4_t __attribute__((__always_inline__, __nodebug__))
__usub8(uint8x4_t __a, uint8x4_t __b) {
  return __builtin_arm_usub8(__a, __b);
}




static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
__usad8(uint8x4_t __a, uint8x4_t __b) {
  return __builtin_arm_usad8(__a, __b);
}
static __inline__ uint32_t __attribute__((__always_inline__, __nodebug__))
__usada8(uint8x4_t __a, uint8x4_t __b, uint32_t __c) {
  return __builtin_arm_usada8(__a, __b, __c);
}




static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
__qadd16(int16x2_t __a, int16x2_t __b) {
  return __builtin_arm_qadd16(__a, __b);
}
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
__qasx(int16x2_t __a, int16x2_t __b) {
  return __builtin_arm_qasx(__a, __b);
}
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
__qsax(int16x2_t __a, int16x2_t __b) {
  return __builtin_arm_qsax(__a, __b);
}
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
__qsub16(int16x2_t __a, int16x2_t __b) {
  return __builtin_arm_qsub16(__a, __b);
}
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
__sadd16(int16x2_t __a, int16x2_t __b) {
  return __builtin_arm_sadd16(__a, __b);
}
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
__sasx(int16x2_t __a, int16x2_t __b) {
  return __builtin_arm_sasx(__a, __b);
}
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
__shadd16(int16x2_t __a, int16x2_t __b) {
  return __builtin_arm_shadd16(__a, __b);
}
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
__shasx(int16x2_t __a, int16x2_t __b) {
  return __builtin_arm_shasx(__a, __b);
}
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
__shsax(int16x2_t __a, int16x2_t __b) {
  return __builtin_arm_shsax(__a, __b);
}
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
__shsub16(int16x2_t __a, int16x2_t __b) {
  return __builtin_arm_shsub16(__a, __b);
}
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
__ssax(int16x2_t __a, int16x2_t __b) {
  return __builtin_arm_ssax(__a, __b);
}
static __inline__ int16x2_t __attribute__((__always_inline__, __nodebug__))
__ssub16(int16x2_t __a, int16x2_t __b) {
  return __builtin_arm_ssub16(__a, __b);
}
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
__uadd16(uint16x2_t __a, uint16x2_t __b) {
  return __builtin_arm_uadd16(__a, __b);
}
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
__uasx(uint16x2_t __a, uint16x2_t __b) {
  return __builtin_arm_uasx(__a, __b);
}
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
__uhadd16(uint16x2_t __a, uint16x2_t __b) {
  return __builtin_arm_uhadd16(__a, __b);
}
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
__uhasx(uint16x2_t __a, uint16x2_t __b) {
  return __builtin_arm_uhasx(__a, __b);
}
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
__uhsax(uint16x2_t __a, uint16x2_t __b) {
  return __builtin_arm_uhsax(__a, __b);
}
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
__uhsub16(uint16x2_t __a, uint16x2_t __b) {
  return __builtin_arm_uhsub16(__a, __b);
}
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
__uqadd16(uint16x2_t __a, uint16x2_t __b) {
  return __builtin_arm_uqadd16(__a, __b);
}
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
__uqasx(uint16x2_t __a, uint16x2_t __b) {
  return __builtin_arm_uqasx(__a, __b);
}
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
__uqsax(uint16x2_t __a, uint16x2_t __b) {
  return __builtin_arm_uqsax(__a, __b);
}
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
__uqsub16(uint16x2_t __a, uint16x2_t __b) {
  return __builtin_arm_uqsub16(__a, __b);
}
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
__usax(uint16x2_t __a, uint16x2_t __b) {
  return __builtin_arm_usax(__a, __b);
}
static __inline__ uint16x2_t __attribute__((__always_inline__, __nodebug__))
__usub16(uint16x2_t __a, uint16x2_t __b) {
  return __builtin_arm_usub16(__a, __b);
}




static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
__smlad(int16x2_t __a, int16x2_t __b, int32_t __c) {
  return __builtin_arm_smlad(__a, __b, __c);
}
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
__smladx(int16x2_t __a, int16x2_t __b, int32_t __c) {
  return __builtin_arm_smladx(__a, __b, __c);
}
static __inline__ int64_t __attribute__((__always_inline__, __nodebug__))
__smlald(int16x2_t __a, int16x2_t __b, int64_t __c) {
  return __builtin_arm_smlald(__a, __b, __c);
}
static __inline__ int64_t __attribute__((__always_inline__, __nodebug__))
__smlaldx(int16x2_t __a, int16x2_t __b, int64_t __c) {
  return __builtin_arm_smlaldx(__a, __b, __c);
}
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
__smlsd(int16x2_t __a, int16x2_t __b, int32_t __c) {
  return __builtin_arm_smlsd(__a, __b, __c);
}
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
__smlsdx(int16x2_t __a, int16x2_t __b, int32_t __c) {
  return __builtin_arm_smlsdx(__a, __b, __c);
}
static __inline__ int64_t __attribute__((__always_inline__, __nodebug__))
__smlsld(int16x2_t __a, int16x2_t __b, int64_t __c) {
  return __builtin_arm_smlsld(__a, __b, __c);
}
static __inline__ int64_t __attribute__((__always_inline__, __nodebug__))
__smlsldx(int16x2_t __a, int16x2_t __b, int64_t __c) {
  return __builtin_arm_smlsldx(__a, __b, __c);
}
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
__smuad(int16x2_t __a, int16x2_t __b) {
  return __builtin_arm_smuad(__a, __b);
}
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
__smuadx(int16x2_t __a, int16x2_t __b) {
  return __builtin_arm_smuadx(__a, __b);
}
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
__smusd(int16x2_t __a, int16x2_t __b) {
  return __builtin_arm_smusd(__a, __b);
}
static __inline__ int32_t __attribute__((__always_inline__, __nodebug__))
__smusdx(int16x2_t __a, int16x2_t __b) {
  return __builtin_arm_smusdx(__a, __b);
}
# 8 "C:\\Keil_v5\\ARM\\ARMCLANG\\bin\\..\\include\\arm_compat.h" 2 3
# 40 "C:\\Keil_v5\\ARM\\ARMCLANG\\bin\\..\\include\\arm_compat.h" 3
static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__disable_fiq(void) {
  unsigned int cpsr;

  __asm__ __volatile__("mrs %[cpsr], faultmask\n"
                       "cpsid f\n"
                       : [cpsr] "=r"(cpsr));
  return cpsr & 0x1;
# 62 "C:\\Keil_v5\\ARM\\ARMCLANG\\bin\\..\\include\\arm_compat.h" 3
}


static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__disable_irq(void) {
  unsigned int cpsr;


  __asm__ __volatile__("mrs %[cpsr], primask\n"
                       "cpsid i\n"
                       : [cpsr] "=r"(cpsr));
  return cpsr & 0x1;
# 89 "C:\\Keil_v5\\ARM\\ARMCLANG\\bin\\..\\include\\arm_compat.h" 3
}







static __inline__ void __attribute__((__always_inline__, __nodebug__))
__enable_fiq(void) {

  __asm__ __volatile__("cpsie f");
# 109 "C:\\Keil_v5\\ARM\\ARMCLANG\\bin\\..\\include\\arm_compat.h" 3
}


static __inline__ void __attribute__((__always_inline__, __nodebug__))
__enable_irq(void) {

  __asm__ __volatile__("cpsie i");
# 124 "C:\\Keil_v5\\ARM\\ARMCLANG\\bin\\..\\include\\arm_compat.h" 3
}

static __inline__ void __attribute__((__always_inline__, __nodebug__)) __force_stores(void) {
    __asm__ __volatile__ ("" : : : "memory", "cc");
}

static void __attribute__((__always_inline__, __nodebug__)) __memory_changed(void) {
    __asm__ __volatile__ ("" : : : "memory", "cc");
}

static void __attribute__((__always_inline__, __nodebug__)) __schedule_barrier(void) {
    __asm__ __volatile__ ("" : : : "memory", "cc");
}

static __inline__ int __attribute__((__always_inline__, __nodebug__))
__semihost(int val, const void *ptr) {
  register int v __asm__("r0") = val;
  register const void *p __asm__("r1") = ptr;
  __asm__ __volatile__(


      "bkpt 0xab"
# 160 "C:\\Keil_v5\\ARM\\ARMCLANG\\bin\\..\\include\\arm_compat.h" 3
      : "+r"(v), "+r"(p)
      :
      : "memory", "cc");
  return v;
}


static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
__vfp_status(unsigned int mask, unsigned int flags) {
  unsigned int fpscr;
  __asm__ __volatile__("vmrs %[fpscr], fpscr" : [fpscr] "=r"(fpscr));
  unsigned int set = mask & flags;
  unsigned int clear = mask & ~flags;
  unsigned int toggle = ~mask & flags;
  fpscr |= set;
  fpscr &= ~clear;
  fpscr ^= toggle;
  __asm__ __volatile__("vmsr fpscr, %[fpscr]" : : [fpscr] "r"(fpscr));
  return fpscr;
}
# 34 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 2 3
# 68 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"

  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#pragma clang diagnostic pop



#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"

  struct __attribute__((packed, aligned(1))) T_UINT16_WRITE { uint16_t v; };
#pragma clang diagnostic pop



#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"

  struct __attribute__((packed, aligned(1))) T_UINT16_READ { uint16_t v; };
#pragma clang diagnostic pop



#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"

  struct __attribute__((packed, aligned(1))) T_UINT32_WRITE { uint32_t v; };
#pragma clang diagnostic pop



#pragma clang diagnostic push
#pragma clang diagnostic ignored "-Wpacked"

  struct __attribute__((packed, aligned(1))) T_UINT32_READ { uint32_t v; };
#pragma clang diagnostic pop
# 166 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline uint32_t __get_CONTROL(void)
{
  uint32_t result;

  __asm volatile ("MRS %0, control" : "=r" (result) );
  return(result);
}
# 196 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline void __set_CONTROL(uint32_t control)
{
  __asm volatile ("MSR control, %0" : : "r" (control) : "memory");
}
# 220 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline uint32_t __get_IPSR(void)
{
  uint32_t result;

  __asm volatile ("MRS %0, ipsr" : "=r" (result) );
  return(result);
}







__attribute__((always_inline)) static __inline uint32_t __get_APSR(void)
{
  uint32_t result;

  __asm volatile ("MRS %0, apsr" : "=r" (result) );
  return(result);
}







__attribute__((always_inline)) static __inline uint32_t __get_xPSR(void)
{
  uint32_t result;

  __asm volatile ("MRS %0, xpsr" : "=r" (result) );
  return(result);
}







__attribute__((always_inline)) static __inline uint32_t __get_PSP(void)
{
  uint32_t result;

  __asm volatile ("MRS %0, psp" : "=r" (result) );
  return(result);
}
# 292 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline void __set_PSP(uint32_t topOfProcStack)
{
  __asm volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
}
# 316 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline uint32_t __get_MSP(void)
{
  uint32_t result;

  __asm volatile ("MRS %0, msp" : "=r" (result) );
  return(result);
}
# 346 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline void __set_MSP(uint32_t topOfMainStack)
{
  __asm volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
}
# 397 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline uint32_t __get_PRIMASK(void)
{
  uint32_t result;

  __asm volatile ("MRS %0, primask" : "=r" (result) );
  return(result);
}
# 427 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline void __set_PRIMASK(uint32_t priMask)
{
  __asm volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
# 471 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline uint32_t __get_BASEPRI(void)
{
  uint32_t result;

  __asm volatile ("MRS %0, basepri" : "=r" (result) );
  return(result);
}
# 501 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline void __set_BASEPRI(uint32_t basePri)
{
  __asm volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
}
# 526 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline void __set_BASEPRI_MAX(uint32_t basePri)
{
  __asm volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
}







__attribute__((always_inline)) static __inline uint32_t __get_FAULTMASK(void)
{
  uint32_t result;

  __asm volatile ("MRS %0, faultmask" : "=r" (result) );
  return(result);
}
# 567 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline void __set_FAULTMASK(uint32_t faultMask)
{
  __asm volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
# 914 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline uint32_t __ROR(uint32_t op1, uint32_t op2)
{
  op2 %= 32U;
  if (op2 == 0U)
  {
    return op1;
  }
  return (op1 >> op2) | (op1 << (32U - op2));
}
# 949 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline uint8_t __CLZ(uint32_t value)
{
# 960 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
  if (value == 0U)
  {
    return 32U;
  }
  return __builtin_clz(value);
}
# 1079 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline uint32_t __RRX(uint32_t value)
{
  uint32_t result;

  __asm volatile ("rrx %0, %1" : "=r" (result) : "r" (value) );
  return(result);
}
# 1094 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline uint8_t __LDRBT(volatile uint8_t *ptr)
{
  uint32_t result;

  __asm volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
  return ((uint8_t) result);
}
# 1109 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline uint16_t __LDRHT(volatile uint16_t *ptr)
{
  uint32_t result;

  __asm volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
  return ((uint16_t) result);
}
# 1124 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline uint32_t __LDRT(volatile uint32_t *ptr)
{
  uint32_t result;

  __asm volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
  return(result);
}
# 1139 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline void __STRBT(uint8_t value, volatile uint8_t *ptr)
{
  __asm volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
# 1151 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline void __STRHT(uint16_t value, volatile uint16_t *ptr)
{
  __asm volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
}
# 1163 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline void __STRT(uint32_t value, volatile uint32_t *ptr)
{
  __asm volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
}
# 1455 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_armclang.h" 3
__attribute__((always_inline)) static __inline int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
{
  int32_t result;

  __asm volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
  return(result);
}
# 48 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\cmsis_compiler.h" 2 3
# 163 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 2 3
# 264 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
typedef union
{
  struct
  {
    uint32_t _reserved0:16;
    uint32_t GE:4;
    uint32_t _reserved1:7;
    uint32_t Q:1;
    uint32_t V:1;
    uint32_t C:1;
    uint32_t Z:1;
    uint32_t N:1;
  } b;
  uint32_t w;
} APSR_Type;
# 303 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
typedef union
{
  struct
  {
    uint32_t ISR:9;
    uint32_t _reserved0:23;
  } b;
  uint32_t w;
} IPSR_Type;
# 321 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
typedef union
{
  struct
  {
    uint32_t ISR:9;
    uint32_t _reserved0:1;
    uint32_t ICI_IT_1:6;
    uint32_t GE:4;
    uint32_t _reserved1:4;
    uint32_t T:1;
    uint32_t ICI_IT_2:2;
    uint32_t Q:1;
    uint32_t V:1;
    uint32_t C:1;
    uint32_t Z:1;
    uint32_t N:1;
  } b;
  uint32_t w;
} xPSR_Type;
# 376 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
typedef union
{
  struct
  {
    uint32_t nPRIV:1;
    uint32_t SPSEL:1;
    uint32_t FPCA:1;
    uint32_t _reserved0:29;
  } b;
  uint32_t w;
} CONTROL_Type;
# 411 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
typedef struct
{
  volatile uint32_t ISER[8U];
        uint32_t RESERVED0[24U];
  volatile uint32_t ICER[8U];
        uint32_t RESERVED1[24U];
  volatile uint32_t ISPR[8U];
        uint32_t RESERVED2[24U];
  volatile uint32_t ICPR[8U];
        uint32_t RESERVED3[24U];
  volatile uint32_t IABR[8U];
        uint32_t RESERVED4[56U];
  volatile uint8_t IP[240U];
        uint32_t RESERVED5[644U];
  volatile uint32_t STIR;
} NVIC_Type;
# 445 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
typedef struct
{
  volatile const uint32_t CPUID;
  volatile uint32_t ICSR;
  volatile uint32_t VTOR;
  volatile uint32_t AIRCR;
  volatile uint32_t SCR;
  volatile uint32_t CCR;
  volatile uint8_t SHP[12U];
  volatile uint32_t SHCSR;
  volatile uint32_t CFSR;
  volatile uint32_t HFSR;
  volatile uint32_t DFSR;
  volatile uint32_t MMFAR;
  volatile uint32_t BFAR;
  volatile uint32_t AFSR;
  volatile const uint32_t PFR[2U];
  volatile const uint32_t DFR;
  volatile const uint32_t ADR;
  volatile const uint32_t MMFR[4U];
  volatile const uint32_t ISAR[5U];
        uint32_t RESERVED0[5U];
  volatile uint32_t CPACR;
} SCB_Type;
# 724 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
typedef struct
{
        uint32_t RESERVED0[1U];
  volatile const uint32_t ICTR;
  volatile uint32_t ACTLR;
} SCnSCB_Type;
# 764 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
typedef struct
{
  volatile uint32_t CTRL;
  volatile uint32_t LOAD;
  volatile uint32_t VAL;
  volatile const uint32_t CALIB;
} SysTick_Type;
# 816 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
typedef struct
{
  volatile union
  {
    volatile uint8_t u8;
    volatile uint16_t u16;
    volatile uint32_t u32;
  } PORT [32U];
        uint32_t RESERVED0[864U];
  volatile uint32_t TER;
        uint32_t RESERVED1[15U];
  volatile uint32_t TPR;
        uint32_t RESERVED2[15U];
  volatile uint32_t TCR;
        uint32_t RESERVED3[32U];
        uint32_t RESERVED4[43U];
  volatile uint32_t LAR;
  volatile const uint32_t LSR;
        uint32_t RESERVED5[6U];
  volatile const uint32_t PID4;
  volatile const uint32_t PID5;
  volatile const uint32_t PID6;
  volatile const uint32_t PID7;
  volatile const uint32_t PID0;
  volatile const uint32_t PID1;
  volatile const uint32_t PID2;
  volatile const uint32_t PID3;
  volatile const uint32_t CID0;
  volatile const uint32_t CID1;
  volatile const uint32_t CID2;
  volatile const uint32_t CID3;
} ITM_Type;
# 904 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
typedef struct
{
  volatile uint32_t CTRL;
  volatile uint32_t CYCCNT;
  volatile uint32_t CPICNT;
  volatile uint32_t EXCCNT;
  volatile uint32_t SLEEPCNT;
  volatile uint32_t LSUCNT;
  volatile uint32_t FOLDCNT;
  volatile const uint32_t PCSR;
  volatile uint32_t COMP0;
  volatile uint32_t MASK0;
  volatile uint32_t FUNCTION0;
        uint32_t RESERVED0[1U];
  volatile uint32_t COMP1;
  volatile uint32_t MASK1;
  volatile uint32_t FUNCTION1;
        uint32_t RESERVED1[1U];
  volatile uint32_t COMP2;
  volatile uint32_t MASK2;
  volatile uint32_t FUNCTION2;
        uint32_t RESERVED2[1U];
  volatile uint32_t COMP3;
  volatile uint32_t MASK3;
  volatile uint32_t FUNCTION3;
} DWT_Type;
# 1051 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
typedef struct
{
  volatile const uint32_t SSPSR;
  volatile uint32_t CSPSR;
        uint32_t RESERVED0[2U];
  volatile uint32_t ACPR;
        uint32_t RESERVED1[55U];
  volatile uint32_t SPPR;
        uint32_t RESERVED2[131U];
  volatile const uint32_t FFSR;
  volatile uint32_t FFCR;
  volatile const uint32_t FSCR;
        uint32_t RESERVED3[759U];
  volatile const uint32_t TRIGGER;
  volatile const uint32_t FIFO0;
  volatile const uint32_t ITATBCTR2;
        uint32_t RESERVED4[1U];
  volatile const uint32_t ITATBCTR0;
  volatile const uint32_t FIFO1;
  volatile uint32_t ITCTRL;
        uint32_t RESERVED5[39U];
  volatile uint32_t CLAIMSET;
  volatile uint32_t CLAIMCLR;
        uint32_t RESERVED7[8U];
  volatile const uint32_t DEVID;
  volatile const uint32_t DEVTYPE;
} TPI_Type;
# 1213 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
typedef struct
{
  volatile const uint32_t TYPE;
  volatile uint32_t CTRL;
  volatile uint32_t RNR;
  volatile uint32_t RBAR;
  volatile uint32_t RASR;
  volatile uint32_t RBAR_A1;
  volatile uint32_t RASR_A1;
  volatile uint32_t RBAR_A2;
  volatile uint32_t RASR_A2;
  volatile uint32_t RBAR_A3;
  volatile uint32_t RASR_A3;
} MPU_Type;
# 1309 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
typedef struct
{
        uint32_t RESERVED0[1U];
  volatile uint32_t FPCCR;
  volatile uint32_t FPCAR;
  volatile uint32_t FPDSCR;
  volatile const uint32_t MVFR0;
  volatile const uint32_t MVFR1;
  volatile const uint32_t MVFR2;
} FPU_Type;
# 1421 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
typedef struct
{
  volatile uint32_t DHCSR;
  volatile uint32_t DCRSR;
  volatile uint32_t DCRDR;
  volatile uint32_t DEMCR;
} CoreDebug_Type;
# 1653 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
static __inline void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);

  reg_value = ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR;
  reg_value &= ~((uint32_t)((0xFFFFUL << 16U) | (7UL << 8U)));
  reg_value = (reg_value |
                ((uint32_t)0x5FAUL << 16U) |
                (PriorityGroupTmp << 8U) );
  ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR = reg_value;
}







static __inline uint32_t __NVIC_GetPriorityGrouping(void)
{
  return ((uint32_t)((((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR & (7UL << 8U)) >> 8U));
}
# 1684 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
static __inline void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    __asm volatile("":::"memory");
    ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    __asm volatile("":::"memory");
  }
}
# 1703 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
static __inline uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
  }
  else
  {
    return(0U);
  }
}
# 1722 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
static __inline void __NVIC_DisableIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
    __builtin_arm_dsb(0xF);
    __builtin_arm_isb(0xF);
  }
}
# 1741 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
static __inline uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
  }
  else
  {
    return(0U);
  }
}
# 1760 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
static __inline void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  }
}
# 1775 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
static __inline void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
  }
}
# 1792 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
static __inline uint32_t __NVIC_GetActive(IRQn_Type IRQn)
{
  if ((int32_t)(IRQn) >= 0)
  {
    return((uint32_t)(((((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
  }
  else
  {
    return(0U);
  }
}
# 1814 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
static __inline void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
  if ((int32_t)(IRQn) >= 0)
  {
    ((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - 4)) & (uint32_t)0xFFUL);
  }
  else
  {
    ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - 4)) & (uint32_t)0xFFUL);
  }
}
# 1836 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
static __inline uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
{

  if ((int32_t)(IRQn) >= 0)
  {
    return(((uint32_t)((NVIC_Type *) ((0xE000E000UL) + 0x0100UL) )->IP[((uint32_t)IRQn)] >> (8U - 4)));
  }
  else
  {
    return(((uint32_t)((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - 4)));
  }
}
# 1861 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
static __inline uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(4)) ? (uint32_t)(4) : (uint32_t)(7UL - PriorityGroupTmp);
  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(4)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(4));

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
           ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
         );
}
# 1888 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
static __inline void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
{
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(4)) ? (uint32_t)(4) : (uint32_t)(7UL - PriorityGroupTmp);
  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(4)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(4));

  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
}
# 1911 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
static __inline void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
  uint32_t *vectors = (uint32_t *)((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->VTOR;
  vectors[(int32_t)IRQn + 16] = vector;

}
# 1927 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
static __inline uint32_t __NVIC_GetVector(IRQn_Type IRQn)
{
  uint32_t *vectors = (uint32_t *)((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->VTOR;
  return vectors[(int32_t)IRQn + 16];
}






__attribute__((__noreturn__)) static __inline void __NVIC_SystemReset(void)
{
  __builtin_arm_dsb(0xF);

  ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR = (uint32_t)((0x5FAUL << 16U) |
                           (((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->AIRCR & (7UL << 8U)) |
                            (1UL << 2U) );
  __builtin_arm_dsb(0xF);

  for(;;)
  {
    __builtin_arm_nop();
  }
}
# 1960 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
# 1 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\mpu_armv7.h" 1 3
# 29 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\mpu_armv7.h" 3
# 183 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\mpu_armv7.h" 3
typedef struct {
  uint32_t RBAR;
  uint32_t RASR;
} ARM_MPU_Region_t;




static __inline void ARM_MPU_Enable(uint32_t MPU_Control)
{
  __builtin_arm_dmb(0xF);
  ((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->CTRL = MPU_Control | (1UL );

  ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHCSR |= (1UL << 16U);

  __builtin_arm_dsb(0xF);
  __builtin_arm_isb(0xF);
}



static __inline void ARM_MPU_Disable(void)
{
  __builtin_arm_dmb(0xF);

  ((SCB_Type *) ((0xE000E000UL) + 0x0D00UL) )->SHCSR &= ~(1UL << 16U);

  ((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->CTRL &= ~(1UL );
  __builtin_arm_dsb(0xF);
  __builtin_arm_isb(0xF);
}




static __inline void ARM_MPU_ClrRegion(uint32_t rnr)
{
  ((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RNR = rnr;
  ((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RASR = 0U;
}





static __inline void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
{
  ((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RBAR = rbar;
  ((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RASR = rasr;
}






static __inline void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
{
  ((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RNR = rnr;
  ((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RBAR = rbar;
  ((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RASR = rasr;
}






static __inline void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __restrict src, uint32_t len)
{
  uint32_t i;
  for (i = 0U; i < len; ++i)
  {
    dst[i] = src[i];
  }
}





static __inline void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
{
  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
  while (cnt > 4U) {
    ARM_MPU_OrderedMemcpy(&(((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RBAR), &(table->RBAR), 4U*rowWordSize);
    table += 4U;
    cnt -= 4U;
  }
  ARM_MPU_OrderedMemcpy(&(((MPU_Type *) ((0xE000E000UL) + 0x0D90UL) )->RBAR), &(table->RBAR), cnt*rowWordSize);
}
# 1961 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 2 3
# 1981 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
static __inline uint32_t SCB_GetFPUType(void)
{
  uint32_t mvfr0;

  mvfr0 = ((FPU_Type *) ((0xE000E000UL) + 0x0F30UL) )->MVFR0;
  if ((mvfr0 & ((0xFUL << 4U) | (0xFUL << 8U))) == 0x020U)
  {
    return 1U;
  }
  else
  {
    return 0U;
  }
}
# 2022 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
static __inline uint32_t SysTick_Config(uint32_t ticks)
{
  if ((ticks - 1UL) > (0xFFFFFFUL ))
  {
    return (1UL);
  }

  ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->LOAD = (uint32_t)(ticks - 1UL);
  __NVIC_SetPriority (SysTick_IRQn, (1UL << 4) - 1UL);
  ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->VAL = 0UL;
  ((SysTick_Type *) ((0xE000E000UL) + 0x0010UL) )->CTRL = (1UL << 2U) |
                   (1UL << 1U) |
                   (1UL );
  return (0UL);
}
# 2052 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
extern volatile int32_t ITM_RxBuffer;
# 2064 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
static __inline uint32_t ITM_SendChar (uint32_t ch)
{
  if (((((ITM_Type *) (0xE0000000UL) )->TCR & (1UL )) != 0UL) &&
      ((((ITM_Type *) (0xE0000000UL) )->TER & 1UL ) != 0UL) )
  {
    while (((ITM_Type *) (0xE0000000UL) )->PORT[0U].u32 == 0UL)
    {
      __builtin_arm_nop();
    }
    ((ITM_Type *) (0xE0000000UL) )->PORT[0U].u8 = (uint8_t)ch;
  }
  return (ch);
}
# 2085 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
static __inline int32_t ITM_ReceiveChar (void)
{
  int32_t ch = -1;

  if (ITM_RxBuffer != ((int32_t)0x5AA55AA5U))
  {
    ch = ITM_RxBuffer;
    ITM_RxBuffer = ((int32_t)0x5AA55AA5U);
  }

  return (ch);
}
# 2105 "../core/AT32F435CGU7/libraries/cmsis/cm4/core_support\\core_cm4.h" 3
static __inline int32_t ITM_CheckChar (void)
{

  if (ITM_RxBuffer == ((int32_t)0x5AA55AA5U))
  {
    return (0);
  }
  else
  {
    return (1);
  }
}
# 332 "../core/AT32F435CGU7/libraries/cmsis/cm4/device_support\\at32f435_437.h" 2
# 1 "../core/AT32F435CGU7/libraries/cmsis/cm4/device_support\\system_at32f435_437.h" 1
# 47 "../core/AT32F435CGU7/libraries/cmsis/cm4/device_support\\system_at32f435_437.h"
extern unsigned int system_core_clock;
# 57 "../core/AT32F435CGU7/libraries/cmsis/cm4/device_support\\system_at32f435_437.h"
extern void SystemInit(void);
extern void system_core_clock_update(void);
# 333 "../core/AT32F435CGU7/libraries/cmsis/cm4/device_support\\at32f435_437.h" 2






typedef int32_t INT32;
typedef int16_t INT16;
typedef int8_t INT8;
typedef uint32_t UINT32;
typedef uint16_t UINT16;
typedef uint8_t UINT8;

typedef int32_t s32;
typedef int16_t s16;
typedef int8_t s8;

typedef const int32_t sc32;
typedef const int16_t sc16;
typedef const int8_t sc8;

typedef volatile int32_t vs32;
typedef volatile int16_t vs16;
typedef volatile int8_t vs8;

typedef volatile const int32_t vsc32;
typedef volatile const int16_t vsc16;
typedef volatile const int8_t vsc8;

typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;

typedef const uint32_t uc32;
typedef const uint16_t uc16;
typedef const uint8_t uc8;

typedef volatile uint32_t vu32;
typedef volatile uint16_t vu16;
typedef volatile uint8_t vu8;

typedef volatile const uint32_t vuc32;
typedef volatile const uint16_t vuc16;
typedef volatile const uint8_t vuc8;

typedef enum {RESET = 0, SET = !RESET} flag_status;
typedef enum {FALSE = 0, TRUE = !FALSE} confirm_state;
typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
# 772 "../core/AT32F435CGU7/libraries/cmsis/cm4/device_support\\at32f435_437.h"
# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_def.h" 1
# 773 "../core/AT32F435CGU7/libraries/cmsis/cm4/device_support\\at32f435_437.h" 2
# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 1
# 774 "../core/AT32F435CGU7/libraries/cmsis/cm4/device_support\\at32f435_437.h" 2
# 38 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_crm.h" 2
# 101 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_crm.h"
typedef enum
{


  CRM_GPIOA_PERIPH_CLOCK = (((0x30) << 16) | (0 & 0x1f)),
  CRM_GPIOB_PERIPH_CLOCK = (((0x30) << 16) | (1 & 0x1f)),
  CRM_GPIOC_PERIPH_CLOCK = (((0x30) << 16) | (2 & 0x1f)),
  CRM_GPIOD_PERIPH_CLOCK = (((0x30) << 16) | (3 & 0x1f)),
  CRM_GPIOE_PERIPH_CLOCK = (((0x30) << 16) | (4 & 0x1f)),
  CRM_GPIOF_PERIPH_CLOCK = (((0x30) << 16) | (5 & 0x1f)),
  CRM_GPIOG_PERIPH_CLOCK = (((0x30) << 16) | (6 & 0x1f)),
  CRM_GPIOH_PERIPH_CLOCK = (((0x30) << 16) | (7 & 0x1f)),
  CRM_CRC_PERIPH_CLOCK = (((0x30) << 16) | (12 & 0x1f)),
  CRM_EDMA_PERIPH_CLOCK = (((0x30) << 16) | (21 & 0x1f)),
  CRM_DMA1_PERIPH_CLOCK = (((0x30) << 16) | (22 & 0x1f)),
  CRM_DMA2_PERIPH_CLOCK = (((0x30) << 16) | (24 & 0x1f)),
  CRM_OTGFS2_PERIPH_CLOCK = (((0x30) << 16) | (29 & 0x1f)),

  CRM_DVP_PERIPH_CLOCK = (((0x34) << 16) | (0 & 0x1f)),
  CRM_OTGFS1_PERIPH_CLOCK = (((0x34) << 16) | (7 & 0x1f)),
  CRM_SDIO1_PERIPH_CLOCK = (((0x34) << 16) | (15 & 0x1f)),

  CRM_XMC_PERIPH_CLOCK = (((0x38) << 16) | (0 & 0x1f)),
  CRM_QSPI1_PERIPH_CLOCK = (((0x38) << 16) | (1 & 0x1f)),
  CRM_QSPI2_PERIPH_CLOCK = (((0x38) << 16) | (14 & 0x1f)),
  CRM_SDIO2_PERIPH_CLOCK = (((0x38) << 16) | (15 & 0x1f)),

  CRM_TMR2_PERIPH_CLOCK = (((0x40) << 16) | (0 & 0x1f)),
  CRM_TMR3_PERIPH_CLOCK = (((0x40) << 16) | (1 & 0x1f)),
  CRM_TMR4_PERIPH_CLOCK = (((0x40) << 16) | (2 & 0x1f)),
  CRM_TMR5_PERIPH_CLOCK = (((0x40) << 16) | (3 & 0x1f)),
  CRM_TMR6_PERIPH_CLOCK = (((0x40) << 16) | (4 & 0x1f)),
  CRM_TMR7_PERIPH_CLOCK = (((0x40) << 16) | (5 & 0x1f)),
  CRM_TMR12_PERIPH_CLOCK = (((0x40) << 16) | (6 & 0x1f)),
  CRM_TMR13_PERIPH_CLOCK = (((0x40) << 16) | (7 & 0x1f)),
  CRM_TMR14_PERIPH_CLOCK = (((0x40) << 16) | (8 & 0x1f)),
  CRM_WWDT_PERIPH_CLOCK = (((0x40) << 16) | (11 & 0x1f)),
  CRM_SPI2_PERIPH_CLOCK = (((0x40) << 16) | (14 & 0x1f)),
  CRM_SPI3_PERIPH_CLOCK = (((0x40) << 16) | (15 & 0x1f)),
  CRM_USART2_PERIPH_CLOCK = (((0x40) << 16) | (17 & 0x1f)),
  CRM_USART3_PERIPH_CLOCK = (((0x40) << 16) | (18 & 0x1f)),
  CRM_UART4_PERIPH_CLOCK = (((0x40) << 16) | (19 & 0x1f)),
  CRM_UART5_PERIPH_CLOCK = (((0x40) << 16) | (20 & 0x1f)),
  CRM_I2C1_PERIPH_CLOCK = (((0x40) << 16) | (21 & 0x1f)),
  CRM_I2C2_PERIPH_CLOCK = (((0x40) << 16) | (22 & 0x1f)),
  CRM_I2C3_PERIPH_CLOCK = (((0x40) << 16) | (23 & 0x1f)),
  CRM_CAN1_PERIPH_CLOCK = (((0x40) << 16) | (25 & 0x1f)),
  CRM_CAN2_PERIPH_CLOCK = (((0x40) << 16) | (26 & 0x1f)),
  CRM_PWC_PERIPH_CLOCK = (((0x40) << 16) | (28 & 0x1f)),
  CRM_DAC_PERIPH_CLOCK = (((0x40) << 16) | (29 & 0x1f)),
  CRM_UART7_PERIPH_CLOCK = (((0x40) << 16) | (30 & 0x1f)),
  CRM_UART8_PERIPH_CLOCK = (((0x40) << 16) | (31 & 0x1f)),

  CRM_TMR1_PERIPH_CLOCK = (((0x44) << 16) | (0 & 0x1f)),
  CRM_TMR8_PERIPH_CLOCK = (((0x44) << 16) | (1 & 0x1f)),
  CRM_USART1_PERIPH_CLOCK = (((0x44) << 16) | (4 & 0x1f)),
  CRM_USART6_PERIPH_CLOCK = (((0x44) << 16) | (5 & 0x1f)),
  CRM_ADC1_PERIPH_CLOCK = (((0x44) << 16) | (8 & 0x1f)),
  CRM_ADC2_PERIPH_CLOCK = (((0x44) << 16) | (9 & 0x1f)),
  CRM_ADC3_PERIPH_CLOCK = (((0x44) << 16) | (10 & 0x1f)),
  CRM_SPI1_PERIPH_CLOCK = (((0x44) << 16) | (12 & 0x1f)),
  CRM_SPI4_PERIPH_CLOCK = (((0x44) << 16) | (13 & 0x1f)),
  CRM_SCFG_PERIPH_CLOCK = (((0x44) << 16) | (14 & 0x1f)),
  CRM_TMR9_PERIPH_CLOCK = (((0x44) << 16) | (16 & 0x1f)),
  CRM_TMR10_PERIPH_CLOCK = (((0x44) << 16) | (17 & 0x1f)),
  CRM_TMR11_PERIPH_CLOCK = (((0x44) << 16) | (18 & 0x1f)),
  CRM_TMR20_PERIPH_CLOCK = (((0x44) << 16) | (20 & 0x1f)),
  CRM_ACC_PERIPH_CLOCK = (((0x44) << 16) | (29 & 0x1f))
# 243 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_crm.h"
} crm_periph_clock_type;




typedef enum
{


  CRM_GPIOA_PERIPH_RESET = (((0x10) << 16) | (0 & 0x1f)),
  CRM_GPIOB_PERIPH_RESET = (((0x10) << 16) | (1 & 0x1f)),
  CRM_GPIOC_PERIPH_RESET = (((0x10) << 16) | (2 & 0x1f)),
  CRM_GPIOD_PERIPH_RESET = (((0x10) << 16) | (3 & 0x1f)),
  CRM_GPIOE_PERIPH_RESET = (((0x10) << 16) | (4 & 0x1f)),
  CRM_GPIOF_PERIPH_RESET = (((0x10) << 16) | (5 & 0x1f)),
  CRM_GPIOG_PERIPH_RESET = (((0x10) << 16) | (6 & 0x1f)),
  CRM_GPIOH_PERIPH_RESET = (((0x10) << 16) | (7 & 0x1f)),
  CRM_CRC_PERIPH_RESET = (((0x10) << 16) | (12 & 0x1f)),
  CRM_EDMA_PERIPH_RESET = (((0x10) << 16) | (21 & 0x1f)),
  CRM_DMA1_PERIPH_RESET = (((0x10) << 16) | (22 & 0x1f)),
  CRM_DMA2_PERIPH_RESET = (((0x10) << 16) | (24 & 0x1f)),
  CRM_OTGFS2_PERIPH_RESET = (((0x10) << 16) | (29 & 0x1f)),

  CRM_DVP_PERIPH_RESET = (((0x14) << 16) | (0 & 0x1f)),
  CRM_OTGFS1_PERIPH_RESET = (((0x14) << 16) | (7 & 0x1f)),
  CRM_SDIO1_PERIPH_RESET = (((0x14) << 16) | (15 & 0x1f)),

  CRM_XMC_PERIPH_RESET = (((0x18) << 16) | (0 & 0x1f)),
  CRM_QSPI1_PERIPH_RESET = (((0x18) << 16) | (1 & 0x1f)),
  CRM_QSPI2_PERIPH_RESET = (((0x18) << 16) | (14 & 0x1f)),
  CRM_SDIO2_PERIPH_RESET = (((0x18) << 16) | (15 & 0x1f)),

  CRM_TMR2_PERIPH_RESET = (((0x20) << 16) | (0 & 0x1f)),
  CRM_TMR3_PERIPH_RESET = (((0x20) << 16) | (1 & 0x1f)),
  CRM_TMR4_PERIPH_RESET = (((0x20) << 16) | (2 & 0x1f)),
  CRM_TMR5_PERIPH_RESET = (((0x20) << 16) | (3 & 0x1f)),
  CRM_TMR6_PERIPH_RESET = (((0x20) << 16) | (4 & 0x1f)),
  CRM_TMR7_PERIPH_RESET = (((0x20) << 16) | (5 & 0x1f)),
  CRM_TMR12_PERIPH_RESET = (((0x20) << 16) | (6 & 0x1f)),
  CRM_TMR13_PERIPH_RESET = (((0x20) << 16) | (7 & 0x1f)),
  CRM_TMR14_PERIPH_RESET = (((0x20) << 16) | (8 & 0x1f)),
  CRM_WWDT_PERIPH_RESET = (((0x20) << 16) | (11 & 0x1f)),
  CRM_SPI2_PERIPH_RESET = (((0x20) << 16) | (14 & 0x1f)),
  CRM_SPI3_PERIPH_RESET = (((0x20) << 16) | (15 & 0x1f)),
  CRM_USART2_PERIPH_RESET = (((0x20) << 16) | (17 & 0x1f)),
  CRM_USART3_PERIPH_RESET = (((0x20) << 16) | (18 & 0x1f)),
  CRM_UART4_PERIPH_RESET = (((0x20) << 16) | (19 & 0x1f)),
  CRM_UART5_PERIPH_RESET = (((0x20) << 16) | (20 & 0x1f)),
  CRM_I2C1_PERIPH_RESET = (((0x20) << 16) | (21 & 0x1f)),
  CRM_I2C2_PERIPH_RESET = (((0x20) << 16) | (22 & 0x1f)),
  CRM_I2C3_PERIPH_RESET = (((0x20) << 16) | (23 & 0x1f)),
  CRM_CAN1_PERIPH_RESET = (((0x20) << 16) | (25 & 0x1f)),
  CRM_CAN2_PERIPH_RESET = (((0x20) << 16) | (26 & 0x1f)),
  CRM_PWC_PERIPH_RESET = (((0x20) << 16) | (28 & 0x1f)),
  CRM_DAC_PERIPH_RESET = (((0x20) << 16) | (29 & 0x1f)),
  CRM_UART7_PERIPH_RESET = (((0x20) << 16) | (30 & 0x1f)),
  CRM_UART8_PERIPH_RESET = (((0x20) << 16) | (31 & 0x1f)),

  CRM_TMR1_PERIPH_RESET = (((0x24) << 16) | (0 & 0x1f)),
  CRM_TMR8_PERIPH_RESET = (((0x24) << 16) | (1 & 0x1f)),
  CRM_USART1_PERIPH_RESET = (((0x24) << 16) | (4 & 0x1f)),
  CRM_USART6_PERIPH_RESET = (((0x24) << 16) | (5 & 0x1f)),
  CRM_ADC_PERIPH_RESET = (((0x24) << 16) | (8 & 0x1f)),
  CRM_SPI1_PERIPH_RESET = (((0x24) << 16) | (12 & 0x1f)),
  CRM_SPI4_PERIPH_RESET = (((0x24) << 16) | (13 & 0x1f)),
  CRM_SCFG_PERIPH_RESET = (((0x24) << 16) | (14 & 0x1f)),
  CRM_TMR9_PERIPH_RESET = (((0x24) << 16) | (16 & 0x1f)),
  CRM_TMR10_PERIPH_RESET = (((0x24) << 16) | (17 & 0x1f)),
  CRM_TMR11_PERIPH_RESET = (((0x24) << 16) | (18 & 0x1f)),
  CRM_TMR20_PERIPH_RESET = (((0x24) << 16) | (20 & 0x1f)),
  CRM_ACC_PERIPH_RESET = (((0x24) << 16) | (29 & 0x1f))
# 383 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_crm.h"
} crm_periph_reset_type;




typedef enum
{


  CRM_GPIOA_PERIPH_LOWPOWER = (((0x50) << 16) | (0 & 0x1f)),
  CRM_GPIOB_PERIPH_LOWPOWER = (((0x50) << 16) | (1 & 0x1f)),
  CRM_GPIOC_PERIPH_LOWPOWER = (((0x50) << 16) | (2 & 0x1f)),
  CRM_GPIOD_PERIPH_LOWPOWER = (((0x50) << 16) | (3 & 0x1f)),
  CRM_GPIOE_PERIPH_LOWPOWER = (((0x50) << 16) | (4 & 0x1f)),
  CRM_GPIOF_PERIPH_LOWPOWER = (((0x50) << 16) | (5 & 0x1f)),
  CRM_GPIOG_PERIPH_LOWPOWER = (((0x50) << 16) | (6 & 0x1f)),
  CRM_GPIOH_PERIPH_LOWPOWER = (((0x50) << 16) | (7 & 0x1f)),
  CRM_CRC_PERIPH_LOWPOWER = (((0x50) << 16) | (12 & 0x1f)),
  CRM_FLASH_PERIPH_LOWPOWER = (((0x50) << 16) | (15 & 0x1f)),
  CRM_SRAM1_PERIPH_LOWPOWER = (((0x50) << 16) | (16 & 0x1f)),
  CRM_SRAM2_PERIPH_LOWPOWER = (((0x50) << 16) | (17 & 0x1f)),
  CRM_EDMA_PERIPH_LOWPOWER = (((0x50) << 16) | (21 & 0x1f)),
  CRM_DMA1_PERIPH_LOWPOWER = (((0x50) << 16) | (22 & 0x1f)),
  CRM_DMA2_PERIPH_LOWPOWER = (((0x50) << 16) | (24 & 0x1f)),
  CRM_EMAC_PERIPH_LOWPOWER = (((0x50) << 16) | (25 & 0x1f)),
  CRM_EMACTX_PERIPH_LOWPOWER = (((0x50) << 16) | (26 & 0x1f)),
  CRM_EMACRX_PERIPH_LOWPOWER = (((0x50) << 16) | (27 & 0x1f)),
  CRM_EMACPTP_PERIPH_LOWPOWER = (((0x50) << 16) | (28 & 0x1f)),
  CRM_OTGFS2_PERIPH_LOWPOWER = (((0x50) << 16) | (29 & 0x1f)),

  CRM_DVP_PERIPH_LOWPOWER = (((0x54) << 16) | (0 & 0x1f)),
  CRM_OTGFS1_PERIPH_LOWPOWER = (((0x54) << 16) | (7 & 0x1f)),
  CRM_SDIO1_PERIPH_LOWPOWER = (((0x54) << 16) | (15 & 0x1f)),

  CRM_XMC_PERIPH_LOWPOWER = (((0x58) << 16) | (0 & 0x1f)),
  CRM_QSPI1_PERIPH_LOWPOWER = (((0x58) << 16) | (1 & 0x1f)),
  CRM_QSPI2_PERIPH_LOWPOWER = (((0x58) << 16) | (14 & 0x1f)),
  CRM_SDIO2_PERIPH_LOWPOWER = (((0x58) << 16) | (15 & 0x1f)),

  CRM_TMR2_PERIPH_LOWPOWER = (((0x60) << 16) | (0 & 0x1f)),
  CRM_TMR3_PERIPH_LOWPOWER = (((0x60) << 16) | (1 & 0x1f)),
  CRM_TMR4_PERIPH_LOWPOWER = (((0x60) << 16) | (2 & 0x1f)),
  CRM_TMR5_PERIPH_LOWPOWER = (((0x60) << 16) | (3 & 0x1f)),
  CRM_TMR6_PERIPH_LOWPOWER = (((0x60) << 16) | (4 & 0x1f)),
  CRM_TMR7_PERIPH_LOWPOWER = (((0x60) << 16) | (5 & 0x1f)),
  CRM_TMR12_PERIPH_LOWPOWER = (((0x60) << 16) | (6 & 0x1f)),
  CRM_TMR13_PERIPH_LOWPOWER = (((0x60) << 16) | (7 & 0x1f)),
  CRM_TMR14_PERIPH_LOWPOWER = (((0x60) << 16) | (8 & 0x1f)),
  CRM_WWDT_PERIPH_LOWPOWER = (((0x60) << 16) | (11 & 0x1f)),
  CRM_SPI2_PERIPH_LOWPOWER = (((0x60) << 16) | (14 & 0x1f)),
  CRM_SPI3_PERIPH_LOWPOWER = (((0x60) << 16) | (15 & 0x1f)),
  CRM_USART2_PERIPH_LOWPOWER = (((0x60) << 16) | (17 & 0x1f)),
  CRM_USART3_PERIPH_LOWPOWER = (((0x60) << 16) | (18 & 0x1f)),
  CRM_UART4_PERIPH_LOWPOWER = (((0x60) << 16) | (19 & 0x1f)),
  CRM_UART5_PERIPH_LOWPOWER = (((0x60) << 16) | (20 & 0x1f)),
  CRM_I2C1_PERIPH_LOWPOWER = (((0x60) << 16) | (21 & 0x1f)),
  CRM_I2C2_PERIPH_LOWPOWER = (((0x60) << 16) | (22 & 0x1f)),
  CRM_I2C3_PERIPH_LOWPOWER = (((0x60) << 16) | (23 & 0x1f)),
  CRM_CAN1_PERIPH_LOWPOWER = (((0x60) << 16) | (25 & 0x1f)),
  CRM_CAN2_PERIPH_LOWPOWER = (((0x60) << 16) | (26 & 0x1f)),
  CRM_PWC_PERIPH_LOWPOWER = (((0x60) << 16) | (28 & 0x1f)),
  CRM_DAC_PERIPH_LOWPOWER = (((0x60) << 16) | (29 & 0x1f)),
  CRM_UART7_PERIPH_LOWPOWER = (((0x60) << 16) | (30 & 0x1f)),
  CRM_UART8_PERIPH_LOWPOWER = (((0x60) << 16) | (31 & 0x1f)),

  CRM_TMR1_PERIPH_LOWPOWER = (((0x64) << 16) | (0 & 0x1f)),
  CRM_TMR8_PERIPH_LOWPOWER = (((0x64) << 16) | (1 & 0x1f)),
  CRM_USART1_PERIPH_LOWPOWER = (((0x64) << 16) | (4 & 0x1f)),
  CRM_USART6_PERIPH_LOWPOWER = (((0x64) << 16) | (5 & 0x1f)),
  CRM_ADC1_PERIPH_LOWPOWER = (((0x64) << 16) | (8 & 0x1f)),
  CRM_ADC2_PERIPH_LOWPOWER = (((0x64) << 16) | (9 & 0x1f)),
  CRM_ADC3_PERIPH_LOWPOWER = (((0x64) << 16) | (10 & 0x1f)),
  CRM_SPI1_PERIPH_LOWPOWER = (((0x64) << 16) | (12 & 0x1f)),
  CRM_SPI4_PERIPH_LOWPOWER = (((0x64) << 16) | (13 & 0x1f)),
  CRM_SCFG_PERIPH_LOWPOWER = (((0x64) << 16) | (14 & 0x1f)),
  CRM_TMR9_PERIPH_LOWPOWER = (((0x64) << 16) | (16 & 0x1f)),
  CRM_TMR10_PERIPH_LOWPOWER = (((0x64) << 16) | (17 & 0x1f)),
  CRM_TMR11_PERIPH_LOWPOWER = (((0x64) << 16) | (18 & 0x1f)),
  CRM_TMR20_PERIPH_LOWPOWER = (((0x64) << 16) | (20 & 0x1f)),
  CRM_ACC_PERIPH_LOWPOWER = (((0x64) << 16) | (29 & 0x1f))
# 536 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_crm.h"
} crm_periph_clock_lowpower_type;




typedef enum
{
  CRM_PLL_SOURCE_HICK = 0x00,
  CRM_PLL_SOURCE_HEXT = 0x01
} crm_pll_clock_source_type;




typedef enum
{
  CRM_PLL_FR_1 = 0x00,
  CRM_PLL_FR_2 = 0x01,
  CRM_PLL_FR_4 = 0x02,
  CRM_PLL_FR_8 = 0x03,
  CRM_PLL_FR_16 = 0x04,
  CRM_PLL_FR_32 = 0x05
} crm_pll_fr_type;




typedef enum
{
  CRM_CLOCK_SOURCE_HICK = 0x00,
  CRM_CLOCK_SOURCE_HEXT = 0x01,
  CRM_CLOCK_SOURCE_PLL = 0x02,
  CRM_CLOCK_SOURCE_LEXT = 0x03,
  CRM_CLOCK_SOURCE_LICK = 0x04
} crm_clock_source_type;




typedef enum
{
  CRM_AHB_DIV_1 = 0x00,
  CRM_AHB_DIV_2 = 0x08,
  CRM_AHB_DIV_4 = 0x09,
  CRM_AHB_DIV_8 = 0x0A,
  CRM_AHB_DIV_16 = 0x0B,
  CRM_AHB_DIV_64 = 0x0C,
  CRM_AHB_DIV_128 = 0x0D,
  CRM_AHB_DIV_256 = 0x0E,
  CRM_AHB_DIV_512 = 0x0F
} crm_ahb_div_type;




typedef enum
{
  CRM_APB1_DIV_1 = 0x00,
  CRM_APB1_DIV_2 = 0x04,
  CRM_APB1_DIV_4 = 0x05,
  CRM_APB1_DIV_8 = 0x06,
  CRM_APB1_DIV_16 = 0x07
} crm_apb1_div_type;




typedef enum
{
  CRM_APB2_DIV_1 = 0x00,
  CRM_APB2_DIV_2 = 0x04,
  CRM_APB2_DIV_4 = 0x05,
  CRM_APB2_DIV_8 = 0x06,
  CRM_APB2_DIV_16 = 0x07
} crm_apb2_div_type;




typedef enum
{
  CRM_USB_DIV_1_5 = 0x00,
  CRM_USB_DIV_1 = 0x01,
  CRM_USB_DIV_2_5 = 0x02,
  CRM_USB_DIV_2 = 0x03,
  CRM_USB_DIV_3_5 = 0x04,
  CRM_USB_DIV_3 = 0x05,
  CRM_USB_DIV_4_5 = 0x06,
  CRM_USB_DIV_4 = 0x07,
  CRM_USB_DIV_5_5 = 0x08,
  CRM_USB_DIV_5 = 0x09,
  CRM_USB_DIV_6_5 = 0x0A,
  CRM_USB_DIV_6 = 0x0B,
  CRM_USB_DIV_7 = 0x0C
} crm_usb_div_type;




typedef enum
{
  CRM_ERTC_CLOCK_NOCLK = 0x000,
  CRM_ERTC_CLOCK_LEXT = 0x001,
  CRM_ERTC_CLOCK_LICK = 0x002,
  CRM_ERTC_CLOCK_HEXT_DIV_2 = 0x023,
  CRM_ERTC_CLOCK_HEXT_DIV_3 = 0x033,
  CRM_ERTC_CLOCK_HEXT_DIV_4 = 0x043,
  CRM_ERTC_CLOCK_HEXT_DIV_5 = 0x053,
  CRM_ERTC_CLOCK_HEXT_DIV_6 = 0x063,
  CRM_ERTC_CLOCK_HEXT_DIV_7 = 0x073,
  CRM_ERTC_CLOCK_HEXT_DIV_8 = 0x083,
  CRM_ERTC_CLOCK_HEXT_DIV_9 = 0x093,
  CRM_ERTC_CLOCK_HEXT_DIV_10 = 0x0A3,
  CRM_ERTC_CLOCK_HEXT_DIV_11 = 0x0B3,
  CRM_ERTC_CLOCK_HEXT_DIV_12 = 0x0C3,
  CRM_ERTC_CLOCK_HEXT_DIV_13 = 0x0D3,
  CRM_ERTC_CLOCK_HEXT_DIV_14 = 0x0E3,
  CRM_ERTC_CLOCK_HEXT_DIV_15 = 0x0F3,
  CRM_ERTC_CLOCK_HEXT_DIV_16 = 0x103,
  CRM_ERTC_CLOCK_HEXT_DIV_17 = 0x113,
  CRM_ERTC_CLOCK_HEXT_DIV_18 = 0x123,
  CRM_ERTC_CLOCK_HEXT_DIV_19 = 0x133,
  CRM_ERTC_CLOCK_HEXT_DIV_20 = 0x143,
  CRM_ERTC_CLOCK_HEXT_DIV_21 = 0x153,
  CRM_ERTC_CLOCK_HEXT_DIV_22 = 0x163,
  CRM_ERTC_CLOCK_HEXT_DIV_23 = 0x173,
  CRM_ERTC_CLOCK_HEXT_DIV_24 = 0x183,
  CRM_ERTC_CLOCK_HEXT_DIV_25 = 0x193,
  CRM_ERTC_CLOCK_HEXT_DIV_26 = 0x1A3,
  CRM_ERTC_CLOCK_HEXT_DIV_27 = 0x1B3,
  CRM_ERTC_CLOCK_HEXT_DIV_28 = 0x1C3,
  CRM_ERTC_CLOCK_HEXT_DIV_29 = 0x1D3,
  CRM_ERTC_CLOCK_HEXT_DIV_30 = 0x1E3,
  CRM_ERTC_CLOCK_HEXT_DIV_31 = 0x1F3
} crm_ertc_clock_type;




typedef enum
{
  CRM_HICK48_DIV6 = 0x00,
  CRM_HICK48_NODIV = 0x01
} crm_hick_div_6_type;




typedef enum
{
  CRM_SCLK_HICK = 0x00,
  CRM_SCLK_HEXT = 0x01,
  CRM_SCLK_PLL = 0x02
} crm_sclk_type;




typedef enum
{
  CRM_CLKOUT_INDEX_1 = 0x00,
  CRM_CLKOUT_INDEX_2 = 0x01
} crm_clkout_index_type;




typedef enum
{
  CRM_CLKOUT1_HICK = 0x00,
  CRM_CLKOUT1_LEXT = 0x01,
  CRM_CLKOUT1_HEXT = 0x02,
  CRM_CLKOUT1_PLL = 0x03
} crm_clkout1_select_type;




typedef enum
{
  CRM_CLKOUT2_SCLK = 0x00,
  CRM_CLKOUT2_HEXT = 0x02,
  CRM_CLKOUT2_PLL = 0x03,
  CRM_CLKOUT2_USB = 0x10,
  CRM_CLKOUT2_ADC = 0x11,
  CRM_CLKOUT2_HICK = 0x12,
  CRM_CLKOUT2_LICK = 0x13,
  CRM_CLKOUT2_LEXT = 0x14
} crm_clkout2_select_type;




typedef enum
{
  CRM_CLKOUT_DIV1_1 = 0x00,
  CRM_CLKOUT_DIV1_2 = 0x04,
  CRM_CLKOUT_DIV1_3 = 0x05,
  CRM_CLKOUT_DIV1_4 = 0x06,
  CRM_CLKOUT_DIV1_5 = 0x07
} crm_clkout_div1_type;




typedef enum
{
  CRM_CLKOUT_DIV2_1 = 0x00,
  CRM_CLKOUT_DIV2_2 = 0x08,
  CRM_CLKOUT_DIV2_4 = 0x09,
  CRM_CLKOUT_DIV2_8 = 0x0A,
  CRM_CLKOUT_DIV2_16 = 0x0B,
  CRM_CLKOUT_DIV2_64 = 0x0C,
  CRM_CLKOUT_DIV2_128 = 0x0D,
  CRM_CLKOUT_DIV2_256 = 0x0E,
  CRM_CLKOUT_DIV2_512 = 0x0F
} crm_clkout_div2_type;




typedef enum
{
  CRM_AUTO_STEP_MODE_DISABLE = 0x00,
  CRM_AUTO_STEP_MODE_ENABLE = 0x03
} crm_auto_step_mode_type;




typedef enum
{
  CRM_USB_CLOCK_SOURCE_PLL = 0x00,
  CRM_USB_CLOCK_SOURCE_HICK = 0x01
} crm_usb_clock_source_type;




typedef enum
{
  CRM_HICK_SCLK_8MHZ = 0x00,
  CRM_HICK_SCLK_48MHZ = 0x01
} crm_hick_sclk_frequency_type;




typedef enum
{
  CRM_EMAC_PULSE_125MS = 0x00,
  CRM_EMAC_PULSE_1SCLK = 0x01
} crm_emac_output_pulse_type;




typedef struct
{
  uint32_t sclk_freq;
  uint32_t ahb_freq;
  uint32_t apb2_freq;
  uint32_t apb1_freq;
} crm_clocks_freq_type;




typedef struct
{



  union
  {
    volatile uint32_t ctrl;
    struct
    {
      volatile uint32_t hicken : 1;
      volatile uint32_t hickstbl : 1;
      volatile uint32_t hicktrim : 6;
      volatile uint32_t hickcal : 8;
      volatile uint32_t hexten : 1;
      volatile uint32_t hextstbl : 1;
      volatile uint32_t hextbyps : 1;
      volatile uint32_t cfden : 1;
      volatile uint32_t reserved1 : 4;
      volatile uint32_t pllen : 1;
      volatile uint32_t pllstbl : 1;
      volatile uint32_t reserved2 : 6;
    } ctrl_bit;
  };




  union
  {
    volatile uint32_t pllcfg;
    struct
    {
      volatile uint32_t pllms : 4;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t pllns : 9;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t pllfr : 3;
      volatile uint32_t reserved3 : 3;
      volatile uint32_t pllrcs : 1;
      volatile uint32_t reserved4 : 9;
    } pllcfg_bit;
  };




  union
  {
    volatile uint32_t cfg;
    struct
    {
      volatile uint32_t sclksel : 2;
      volatile uint32_t sclksts : 2;
      volatile uint32_t ahbdiv : 4;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t apb1div : 3;
      volatile uint32_t apb2div : 3;
      volatile uint32_t ertcdiv : 5;
      volatile uint32_t clkout1_sel : 2;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t clkout1div1 : 3;
      volatile uint32_t clkout2div1 : 3;
      volatile uint32_t clkout2_sel1 : 2;
    } cfg_bit;
  };




  union
  {
    volatile uint32_t clkint;
    struct
    {
      volatile uint32_t lickstblf : 1;
      volatile uint32_t lextstblf : 1;
      volatile uint32_t hickstblf : 1;
      volatile uint32_t hextstblf : 1;
      volatile uint32_t pllstblf : 1;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t cfdf : 1;
      volatile uint32_t lickstblien : 1;
      volatile uint32_t lextstblien : 1;
      volatile uint32_t hickstblien : 1;
      volatile uint32_t hextstblien : 1;
      volatile uint32_t pllstblien : 1;
      volatile uint32_t reserved2 : 3;
      volatile uint32_t lickstblfc : 1;
      volatile uint32_t lextstblfc : 1;
      volatile uint32_t hickstblfc : 1;
      volatile uint32_t hextstblfc : 1;
      volatile uint32_t pllstblfc : 1;
      volatile uint32_t reserved3 : 2;
      volatile uint32_t cfdfc : 1;
      volatile uint32_t reserved4 : 8;
    } clkint_bit;
  };




  union
  {
    volatile uint32_t ahbrst1;

    struct
    {
      volatile uint32_t gpioarst : 1;
      volatile uint32_t gpiobrst : 1;
      volatile uint32_t gpiocrst : 1;
      volatile uint32_t gpiodrst : 1;
      volatile uint32_t gpioerst : 1;
      volatile uint32_t gpiofrst : 1;
      volatile uint32_t gpiogrst : 1;
      volatile uint32_t gpiohrst : 1;
      volatile uint32_t reserved1 : 4;
      volatile uint32_t crcrst : 1;
      volatile uint32_t reserved2 : 8;
      volatile uint32_t edmarst : 1;
      volatile uint32_t dma1rst : 1;
      volatile uint32_t reserved3 : 1;
      volatile uint32_t dma2rst : 1;
      volatile uint32_t reserved4 : 4;
      volatile uint32_t otgfs2rst : 1;
      volatile uint32_t reserved5 : 2;
    } ahbrst1_bit;
# 957 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_crm.h"
  };




  union
  {
    volatile uint32_t ahbrst2;
    struct
    {
      volatile uint32_t dvprst : 1;
      volatile uint32_t reserved1 : 6;
      volatile uint32_t otgfs1rst : 1;
      volatile uint32_t reserved2 : 7;
      volatile uint32_t sdio1rst : 1;
      volatile uint32_t reserved3 : 16;
    } ahbrst2_bit;
  };




  union
  {
    volatile uint32_t ahbrst3;
    struct
    {
      volatile uint32_t xmcrst : 1;
      volatile uint32_t qspi1rst : 1;
      volatile uint32_t reserved1 : 12;
      volatile uint32_t qspi2rst : 1;
      volatile uint32_t sdio2rst : 1;
      volatile uint32_t reserved3 : 16;
    } ahbrst3_bit;
  };




  volatile uint32_t reserved1;




  union
  {
    volatile uint32_t apb1rst;
    struct
    {
      volatile uint32_t tmr2rst : 1;
      volatile uint32_t tmr3rst : 1;
      volatile uint32_t tmr4rst : 1;
      volatile uint32_t tmr5rst : 1;
      volatile uint32_t tmr6rst : 1;
      volatile uint32_t tmr7rst : 1;
      volatile uint32_t tmr12rst : 1;
      volatile uint32_t tmr13rst : 1;
      volatile uint32_t adc14rst : 1;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t wwdtrst : 1;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t spi2rst : 1;
      volatile uint32_t spi3rst : 1;
      volatile uint32_t reserved3 : 1;
      volatile uint32_t usart2rst : 1;
      volatile uint32_t usart3rst : 1;
      volatile uint32_t uart4rst : 1;
      volatile uint32_t uart5rst : 1;
      volatile uint32_t i2c1rst : 1;
      volatile uint32_t i2c2rst : 1;
      volatile uint32_t i2c3rst : 1;
      volatile uint32_t reserved4 : 1;
      volatile uint32_t can1rst : 1;
      volatile uint32_t can2rst : 1;
      volatile uint32_t reserved5 : 1;
      volatile uint32_t pwcrst : 1;
      volatile uint32_t dacrst : 1;
      volatile uint32_t uart7rst : 1;
      volatile uint32_t uart8rst : 1;
    } apb1rst_bit;
  };




  union
  {
    volatile uint32_t apb2rst;
    struct
    {
      volatile uint32_t tmr1rst : 1;
      volatile uint32_t tmr8rst : 1;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t usart1rst : 1;
      volatile uint32_t usart6rst : 1;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t adcrst : 1;
      volatile uint32_t reserved3 : 3;
      volatile uint32_t spi1rst : 1;
      volatile uint32_t spi4rst : 1;
      volatile uint32_t scfgrst : 1;
      volatile uint32_t reserved4 : 1;
      volatile uint32_t tmr9rst : 1;
      volatile uint32_t tmr10rst : 1;
      volatile uint32_t tmr11rst : 1;
      volatile uint32_t reserved5 : 1;
      volatile uint32_t tmr20rst : 1;
      volatile uint32_t reserved6 : 8;
      volatile uint32_t accrst : 1;
      volatile uint32_t reserved7 : 2;
    } apb2rst_bit;
  };




  volatile uint32_t reserved2[2];




  union
  {
    volatile uint32_t ahben1;

    struct
    {
      volatile uint32_t gpioaen : 1;
      volatile uint32_t gpioben : 1;
      volatile uint32_t gpiocen : 1;
      volatile uint32_t gpioden : 1;
      volatile uint32_t gpioeen : 1;
      volatile uint32_t gpiofen : 1;
      volatile uint32_t gpiogen : 1;
      volatile uint32_t gpiohen : 1;
      volatile uint32_t reserved1 : 4;
      volatile uint32_t crcen : 1;
      volatile uint32_t reserved2 : 8;
      volatile uint32_t edmaen : 1;
      volatile uint32_t dma1en : 1;
      volatile uint32_t reserved3 : 1;
      volatile uint32_t dma2en : 1;
      volatile uint32_t reserved4 : 4;
      volatile uint32_t otgfs2en : 1;
      volatile uint32_t reserved5 : 2;
    } ahben1_bit;
# 1129 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_crm.h"
  };




  union
  {
    volatile uint32_t ahben2;
    struct
    {
      volatile uint32_t dvpen : 1;
      volatile uint32_t reserved1 : 6;
      volatile uint32_t otgfs1en : 1;
      volatile uint32_t reserved2 : 7;
      volatile uint32_t sdio1en : 1;
      volatile uint32_t reserved3 : 16;
    } ahben2_bit;
  };




  union
  {
    volatile uint32_t ahben3;
    struct
    {
      volatile uint32_t xmcen : 1;
      volatile uint32_t qspi1en : 1;
      volatile uint32_t reserved1 : 12;
      volatile uint32_t qspi2en : 1;
      volatile uint32_t sdio2en : 1;
      volatile uint32_t reserved3 : 16;
    } ahben3_bit;
  };




  volatile uint32_t reserved3;




  union
  {
    volatile uint32_t apb1en;
    struct
    {
      volatile uint32_t tmr2en : 1;
      volatile uint32_t tmr3en : 1;
      volatile uint32_t tmr4en : 1;
      volatile uint32_t tmr5en : 1;
      volatile uint32_t tmr6en : 1;
      volatile uint32_t tmr7en : 1;
      volatile uint32_t tmr12en : 1;
      volatile uint32_t tmr13en : 1;
      volatile uint32_t adc14en : 1;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t wwdten : 1;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t spi2en : 1;
      volatile uint32_t spi3en : 1;
      volatile uint32_t reserved3 : 1;
      volatile uint32_t usart2en : 1;
      volatile uint32_t usart3en : 1;
      volatile uint32_t uart4en : 1;
      volatile uint32_t uart5en : 1;
      volatile uint32_t i2c1en : 1;
      volatile uint32_t i2c2en : 1;
      volatile uint32_t i2c3en : 1;
      volatile uint32_t reserved4 : 1;
      volatile uint32_t can1en : 1;
      volatile uint32_t can2en : 1;
      volatile uint32_t reserved5 : 1;
      volatile uint32_t pwcen : 1;
      volatile uint32_t dacen : 1;
      volatile uint32_t uart7en : 1;
      volatile uint32_t uart8en : 1;
    } apb1en_bit;
  };




  union
  {
    volatile uint32_t apb2en;
    struct
    {
      volatile uint32_t tmr1en : 1;
      volatile uint32_t tmr8en : 1;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t usart1en : 1;
      volatile uint32_t usart6en : 1;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t adcen : 1;
      volatile uint32_t reserved3 : 3;
      volatile uint32_t spi1en : 1;
      volatile uint32_t spi4en : 1;
      volatile uint32_t scfgen : 1;
      volatile uint32_t reserved4 : 1;
      volatile uint32_t tmr9en : 1;
      volatile uint32_t tmr10en : 1;
      volatile uint32_t tmr11en : 1;
      volatile uint32_t reserved5 : 1;
      volatile uint32_t tmr20en : 1;
      volatile uint32_t reserved6 : 8;
      volatile uint32_t accen : 1;
      volatile uint32_t reserved7 : 2;
    } apb2en_bit;
  };




  volatile uint32_t reserved4[2];




  union
  {
    volatile uint32_t ahblpen1;

    struct
    {
      volatile uint32_t gpioalpen : 1;
      volatile uint32_t gpioblpen : 1;
      volatile uint32_t gpioclpen : 1;
      volatile uint32_t gpiodlpen : 1;
      volatile uint32_t gpioelpen : 1;
      volatile uint32_t gpioflpen : 1;
      volatile uint32_t gpioglpen : 1;
      volatile uint32_t gpiohlpen : 1;
      volatile uint32_t reserved1 : 4;
      volatile uint32_t crclpen : 1;
      volatile uint32_t reserved2 : 8;
      volatile uint32_t edmalpen : 1;
      volatile uint32_t dma1lpen : 1;
      volatile uint32_t reserved3 : 1;
      volatile uint32_t dma2lpen : 1;
      volatile uint32_t reserved4 : 4;
      volatile uint32_t otgfs2lpen : 1;
      volatile uint32_t reserved5 : 2;
    } ahblpen1_bit;
# 1301 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_crm.h"
  };




  union
  {
    volatile uint32_t ahblpen2;
    struct
    {
      volatile uint32_t dvplpen : 1;
      volatile uint32_t reserved1 : 6;
      volatile uint32_t otgfs1lpen : 1;
      volatile uint32_t reserved2 : 7;
      volatile uint32_t sdio1lpen : 1;
      volatile uint32_t reserved3 : 16;
    } ahblpen2_bit;
  };




  union
  {
    volatile uint32_t ahblpen3;
    struct
    {
      volatile uint32_t xmclpen : 1;
      volatile uint32_t qspi1lpen : 1;
      volatile uint32_t reserved1 : 12;
      volatile uint32_t qspi2lpen : 1;
      volatile uint32_t sdio2lpen : 1;
      volatile uint32_t reserved3 : 16;
    } ahblpen3_bit;
  };




  volatile uint32_t reserved5;




  union
  {
    volatile uint32_t apb1lpen;
    struct
    {
      volatile uint32_t tmr2lpen : 1;
      volatile uint32_t tmr3lpen : 1;
      volatile uint32_t tmr4lpen : 1;
      volatile uint32_t tmr5lpen : 1;
      volatile uint32_t tmr6lpen : 1;
      volatile uint32_t tmr7lpen : 1;
      volatile uint32_t tmr12lpen : 1;
      volatile uint32_t tmr13lpen : 1;
      volatile uint32_t adc14lpen : 1;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t wwdtlpen : 1;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t spi2lpen : 1;
      volatile uint32_t spi3lpen : 1;
      volatile uint32_t reserved3 : 1;
      volatile uint32_t usart2lpen : 1;
      volatile uint32_t usart3lpen : 1;
      volatile uint32_t uart4lpen : 1;
      volatile uint32_t uart5lpen : 1;
      volatile uint32_t i2c1lpen : 1;
      volatile uint32_t i2c2lpen : 1;
      volatile uint32_t i2c3lpen : 1;
      volatile uint32_t reserved4 : 1;
      volatile uint32_t can1lpen : 1;
      volatile uint32_t can2lpen : 1;
      volatile uint32_t reserved5 : 1;
      volatile uint32_t pwclpen : 1;
      volatile uint32_t daclpen : 1;
      volatile uint32_t uart7lpen : 1;
      volatile uint32_t uart8lpen : 1;
    } apb1lpen_bit;
  };




  union
  {
    volatile uint32_t apb2lpen;
    struct
    {
      volatile uint32_t tmr1lpen : 1;
      volatile uint32_t tmr8lpen : 1;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t usart1lpen : 1;
      volatile uint32_t usart6lpen : 1;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t adclpen : 1;
      volatile uint32_t reserved3 : 3;
      volatile uint32_t spi1lpen : 1;
      volatile uint32_t spi4lpen : 1;
      volatile uint32_t scfglpen : 1;
      volatile uint32_t reserved4 : 1;
      volatile uint32_t tmr9lpen : 1;
      volatile uint32_t tmr10lpen : 1;
      volatile uint32_t tmr11lpen : 1;
      volatile uint32_t reserved5 : 1;
      volatile uint32_t tmr20lpen : 1;
      volatile uint32_t reserved6 : 8;
      volatile uint32_t acclpen : 1;
      volatile uint32_t reserved7 : 2;
    } apb2lpen_bit;
  };




  volatile uint32_t reserved6[2];




  union
  {
    volatile uint32_t bpdc;
    struct
    {
      volatile uint32_t lexten : 1;
      volatile uint32_t lextstbl : 1;
      volatile uint32_t lextbyps : 1;
      volatile uint32_t reserved1 : 5;
      volatile uint32_t ertcsel : 2;
      volatile uint32_t reserved2 : 5;
      volatile uint32_t ertcen : 1;
      volatile uint32_t bpdrst : 1;
      volatile uint32_t reserved3 : 15;
    } bpdc_bit;
  };




  union
  {
    volatile uint32_t ctrlsts;
    struct
    {
      volatile uint32_t licken : 1;
      volatile uint32_t lickstbl : 1;
      volatile uint32_t reserved1 : 22;
      volatile uint32_t rstfc : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t nrstf : 1;
      volatile uint32_t porrstf : 1;
      volatile uint32_t swrstf : 1;
      volatile uint32_t wdtrstf : 1;
      volatile uint32_t wwdtrstf : 1;
      volatile uint32_t lprstf : 1;
    } ctrlsts_bit;
  };




  volatile uint32_t reserved7[10];




  union
  {
    volatile uint32_t misc1;
    struct
    {
      volatile uint32_t hickcal_key : 8;
      volatile uint32_t reserved1 : 4;
      volatile uint32_t hickdiv : 1;
      volatile uint32_t hick_to_usb : 1;
      volatile uint32_t hick_to_sclk : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t clkout2_sel2 : 4;
      volatile uint32_t reserved3 : 4;
      volatile uint32_t clkout1div2 : 4;
      volatile uint32_t clkout2div2 : 4;
    } misc1_bit;
  };




  union
  {
    volatile uint32_t misc2;
    struct
    {
      volatile uint32_t reserved1 : 4;
      volatile uint32_t auto_step_en : 2;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t clk_to_tmr : 1;
      volatile uint32_t emac_pps_sel : 1;
      volatile uint32_t reserved3 : 2;
      volatile uint32_t usbdiv : 4;
      volatile uint32_t reserved4 : 16;
    } misc2_bit;
  };

} crm_type;
# 1518 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_crm.h"
void crm_reset(void);
void crm_lext_bypass(confirm_state new_state);
void crm_hext_bypass(confirm_state new_state);
flag_status crm_flag_get(uint32_t flag);
error_status crm_hext_stable_wait(void);
void crm_hick_clock_trimming_set(uint8_t trim_value);
void crm_hick_clock_calibration_set(uint8_t cali_value);
void crm_periph_clock_enable(crm_periph_clock_type value, confirm_state new_state);
void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state);
void crm_periph_lowpower_mode_enable(crm_periph_clock_lowpower_type value, confirm_state new_state);
void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state);
void crm_flag_clear(uint32_t flag);
void crm_ertc_clock_select(crm_ertc_clock_type value);
void crm_ertc_clock_enable(confirm_state new_state);
void crm_ahb_div_set(crm_ahb_div_type value);
void crm_apb1_div_set(crm_apb1_div_type value);
void crm_apb2_div_set(crm_apb2_div_type value);
void crm_usb_clock_div_set(crm_usb_div_type value);
void crm_clock_failure_detection_enable(confirm_state new_state);
void crm_battery_powered_domain_reset(confirm_state new_state);
void crm_auto_step_mode_enable(confirm_state new_state);
void crm_hick_divider_select(crm_hick_div_6_type value);
void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value);
void crm_usb_clock_source_select(crm_usb_clock_source_type value);
void crm_clkout_to_tmr10_enable(confirm_state new_state);
void crm_pll_config(crm_pll_clock_source_type clock_source, uint16_t pll_ns, uint16_t pll_ms, crm_pll_fr_type pll_fr);

void crm_sysclk_switch(crm_sclk_type value);
crm_sclk_type crm_sysclk_switch_status_get(void);
void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct);
void crm_clock_out1_set(crm_clkout1_select_type clkout);
void crm_clock_out2_set(crm_clkout2_select_type clkout);
void crm_clkout_div_set(crm_clkout_index_type index, crm_clkout_div1_type div1, crm_clkout_div2_type div2);
void crm_emac_output_pulse_set(crm_emac_output_pulse_type width);
void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state);
error_status crm_pll_parameter_calculate(crm_pll_clock_source_type pll_rcs, uint32_t target_sclk_freq, uint16_t *ret_ms, uint16_t *ret_ns, uint16_t *ret_fr);
# 85 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_tmr.h" 1
# 95 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_tmr.h"
typedef enum
{
  TMR_CLOCK_DIV1 = 0x00,
  TMR_CLOCK_DIV2 = 0x01,
  TMR_CLOCK_DIV4 = 0x02
} tmr_clock_division_type;




typedef enum
{
  TMR_COUNT_UP = 0x00,
  TMR_COUNT_DOWN = 0x01,
  TMR_COUNT_TWO_WAY_1 = 0x02,
  TMR_COUNT_TWO_WAY_2 = 0x04,
  TMR_COUNT_TWO_WAY_3 = 0x06
} tmr_count_mode_type;




typedef enum
{
  TMR_PRIMARY_SEL_RESET = 0x00,
  TMR_PRIMARY_SEL_ENABLE = 0x01,
  TMR_PRIMARY_SEL_OVERFLOW = 0x02,
  TMR_PRIMARY_SEL_COMPARE = 0x03,
  TMR_PRIMARY_SEL_C1ORAW = 0x04,
  TMR_PRIMARY_SEL_C2ORAW = 0x05,
  TMR_PRIMARY_SEL_C3ORAW = 0x06,
  TMR_PRIMARY_SEL_C4ORAW = 0x07
} tmr_primary_select_type;




typedef enum
{
  TMR_SUB_INPUT_SEL_IS0 = 0x00,
  TMR_SUB_INPUT_SEL_IS1 = 0x01,
  TMR_SUB_INPUT_SEL_IS2 = 0x02,
  TMR_SUB_INPUT_SEL_IS3 = 0x03,
  TMR_SUB_INPUT_SEL_C1INC = 0x04,
  TMR_SUB_INPUT_SEL_C1DF1 = 0x05,
  TMR_SUB_INPUT_SEL_C2DF2 = 0x06,
  TMR_SUB_INPUT_SEL_EXTIN = 0x07
} sub_tmr_input_sel_type;




typedef enum
{
  TMR_SUB_MODE_DIABLE = 0x00,
  TMR_SUB_ENCODER_MODE_A = 0x01,
  TMR_SUB_ENCODER_MODE_B = 0x02,
  TMR_SUB_ENCODER_MODE_C = 0x03,
  TMR_SUB_RESET_MODE = 0x04,
  TMR_SUB_HANG_MODE = 0x05,
  TMR_SUB_TRIGGER_MODE = 0x06,
  TMR_SUB_EXTERNAL_CLOCK_MODE_A = 0x07
} tmr_sub_mode_select_type;




typedef enum
{
  TMR_ENCODER_MODE_A = TMR_SUB_ENCODER_MODE_A,
  TMR_ENCODER_MODE_B = TMR_SUB_ENCODER_MODE_B,
  TMR_ENCODER_MODE_C = TMR_SUB_ENCODER_MODE_C
} tmr_encoder_mode_type;




typedef enum
{
  TMR_OUTPUT_CONTROL_OFF = 0x00,
  TMR_OUTPUT_CONTROL_HIGH = 0x01,
  TMR_OUTPUT_CONTROL_LOW = 0x02,
  TMR_OUTPUT_CONTROL_SWITCH = 0x03,
  TMR_OUTPUT_CONTROL_FORCE_LOW = 0x04,
  TMR_OUTPUT_CONTROL_FORCE_HIGH = 0x05,
  TMR_OUTPUT_CONTROL_PWM_MODE_A = 0x06,
  TMR_OUTPUT_CONTROL_PWM_MODE_B = 0x07
} tmr_output_control_mode_type;




typedef enum
{
  TMR_FORCE_OUTPUT_HIGH = TMR_OUTPUT_CONTROL_FORCE_HIGH,
  TMR_FORCE_OUTPUT_LOW = TMR_OUTPUT_CONTROL_FORCE_LOW
} tmr_force_output_type;




typedef enum
{
  TMR_OUTPUT_ACTIVE_HIGH = 0x00,
  TMR_OUTPUT_ACTIVE_LOW = 0x01
} tmr_output_polarity_type;




typedef enum
{
  TMR_INPUT_RISING_EDGE = 0x00,
  TMR_INPUT_FALLING_EDGE = 0x01,
  TMR_INPUT_BOTH_EDGE = 0x03
} tmr_input_polarity_type;




typedef enum
{
  TMR_SELECT_CHANNEL_1 = 0x00,
  TMR_SELECT_CHANNEL_1C = 0x01,
  TMR_SELECT_CHANNEL_2 = 0x02,
  TMR_SELECT_CHANNEL_2C = 0x03,
  TMR_SELECT_CHANNEL_3 = 0x04,
  TMR_SELECT_CHANNEL_3C = 0x05,
  TMR_SELECT_CHANNEL_4 = 0x06,
  TMR_SELECT_CHANNEL_5 = 0x07
} tmr_channel_select_type;




typedef enum
{
  TMR_CHANEL1_CONNECTED_C1IRAW = 0x00,
  TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR = 0x01
} tmr_channel1_input_connected_type;




typedef enum
{
  TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01,
  TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02,
  TMR_CC_CHANNEL_MAPPED_STI = 0x03
} tmr_input_direction_mapped_type;




typedef enum
{
  TMR_CHANNEL_INPUT_DIV_1 = 0x00,
  TMR_CHANNEL_INPUT_DIV_2 = 0x01,
  TMR_CHANNEL_INPUT_DIV_4 = 0x02,
  TMR_CHANNEL_INPUT_DIV_8 = 0x03
} tmr_channel_input_divider_type;




typedef enum
{
  TMR_DMA_REQUEST_BY_CHANNEL = 0x00,
  TMR_DMA_REQUEST_BY_OVERFLOW = 0x01
} tmr_dma_request_source_type;




typedef enum
{
  TMR_OVERFLOW_DMA_REQUEST = 0x00000100,
  TMR_C1_DMA_REQUEST = 0x00000200,
  TMR_C2_DMA_REQUEST = 0x00000400,
  TMR_C3_DMA_REQUEST = 0x00000800,
  TMR_C4_DMA_REQUEST = 0x00001000,
  TMR_HALL_DMA_REQUEST = 0x00002000,
  TMR_TRIGGER_DMA_REQUEST = 0x00004000
} tmr_dma_request_type;




typedef enum
{
  TMR_OVERFLOW_SWTRIG = 0x00000001,
  TMR_C1_SWTRIG = 0x00000002,
  TMR_C2_SWTRIG = 0x00000004,
  TMR_C3_SWTRIG = 0x00000008,
  TMR_C4_SWTRIG = 0x00000010,
  TMR_HALL_SWTRIG = 0x00000020,
  TMR_TRIGGER_SWTRIG = 0x00000040,
  TMR_BRK_SWTRIG = 0x00000080
}tmr_event_trigger_type;




typedef enum
{
  TMR_POLARITY_ACTIVE_HIGH = 0x00,
  TMR_POLARITY_ACTIVE_LOW = 0x01,
  TMR_POLARITY_ACTIVE_BOTH = 0x02
}tmr_polarity_active_type;




typedef enum
{
  TMR_ES_FREQUENCY_DIV_1 = 0x00,
  TMR_ES_FREQUENCY_DIV_2 = 0x01,
  TMR_ES_FREQUENCY_DIV_4 = 0x02,
  TMR_ES_FREQUENCY_DIV_8 = 0x03
}tmr_external_signal_divider_type;




typedef enum
{
  TMR_ES_POLARITY_NON_INVERTED = 0x00,
  TMR_ES_POLARITY_INVERTED = 0x01
}tmr_external_signal_polarity_type;




typedef enum
{
  TMR_DMA_TRANSFER_1BYTE = 0x00,
  TMR_DMA_TRANSFER_2BYTES = 0x01,
  TMR_DMA_TRANSFER_3BYTES = 0x02,
  TMR_DMA_TRANSFER_4BYTES = 0x03,
  TMR_DMA_TRANSFER_5BYTES = 0x04,
  TMR_DMA_TRANSFER_6BYTES = 0x05,
  TMR_DMA_TRANSFER_7BYTES = 0x06,
  TMR_DMA_TRANSFER_8BYTES = 0x07,
  TMR_DMA_TRANSFER_9BYTES = 0x08,
  TMR_DMA_TRANSFER_10BYTES = 0x09,
  TMR_DMA_TRANSFER_11BYTES = 0x0A,
  TMR_DMA_TRANSFER_12BYTES = 0x0B,
  TMR_DMA_TRANSFER_13BYTES = 0x0C,
  TMR_DMA_TRANSFER_14BYTES = 0x0D,
  TMR_DMA_TRANSFER_15BYTES = 0x0E,
  TMR_DMA_TRANSFER_16BYTES = 0x0F,
  TMR_DMA_TRANSFER_17BYTES = 0x10,
  TMR_DMA_TRANSFER_18BYTES = 0x11
}tmr_dma_transfer_length_type;




typedef enum
{
  TMR_CTRL1_ADDRESS = 0x0000,
  TMR_CTRL2_ADDRESS = 0x0001,
  TMR_STCTRL_ADDRESS = 0x0002,
  TMR_IDEN_ADDRESS = 0x0003,
  TMR_ISTS_ADDRESS = 0x0004,
  TMR_SWEVT_ADDRESS = 0x0005,
  TMR_CM1_ADDRESS = 0x0006,
  TMR_CM2_ADDRESS = 0x0007,
  TMR_CCTRL_ADDRESS = 0x0008,
  TMR_CVAL_ADDRESS = 0x0009,
  TMR_DIV_ADDRESS = 0x000A,
  TMR_PR_ADDRESS = 0x000B,
  TMR_RPR_ADDRESS = 0x000C,
  TMR_C1DT_ADDRESS = 0x000D,
  TMR_C2DT_ADDRESS = 0x000E,
  TMR_C3DT_ADDRESS = 0x000F,
  TMR_C4DT_ADDRESS = 0x0010,
  TMR_BRK_ADDRESS = 0x0011,
  TMR_DMACTRL_ADDRESS = 0x0012
}tmr_dma_address_type;




typedef enum
{
  TMR_BRK_INPUT_ACTIVE_LOW = 0x00,
  TMR_BRK_INPUT_ACTIVE_HIGH = 0x01
}tmr_brk_polarity_type;




typedef enum
{
  TMR_WP_OFF = 0x00,
  TMR_WP_LEVEL_3 = 0x01,
  TMR_WP_LEVEL_2 = 0x02,
  TMR_WP_LEVEL_1 = 0x03
}tmr_wp_level_type;




typedef enum
{
  TMR2_TMR8TRGOUT_TMR5_GPIO = 0x00,
  TMR2_PTP_TMR5_LICK = 0x01,
  TMR2_OTG1FS_TMR5_LEXT = 0x02,
  TMR2_OTG2FS_TMR5_ERTC = 0x03
}tmr_input_remap_type ;




typedef struct
{
  tmr_output_control_mode_type oc_mode;
  confirm_state oc_idle_state;
  confirm_state occ_idle_state;
  tmr_output_polarity_type oc_polarity;
  tmr_output_polarity_type occ_polarity;
  confirm_state oc_output_state;
  confirm_state occ_output_state;
} tmr_output_config_type;




typedef struct
{
  tmr_channel_select_type input_channel_select;
  tmr_input_polarity_type input_polarity_select;
  tmr_input_direction_mapped_type input_mapped_select;
  uint8_t input_filter_value;
} tmr_input_config_type;




typedef struct
{
  uint8_t deadtime;
  tmr_brk_polarity_type brk_polarity;
  tmr_wp_level_type wp_level;
  confirm_state auto_output_enable;
  confirm_state fcsoen_state;
  confirm_state fcsodis_state;
  confirm_state brk_enable;
} tmr_brkdt_config_type;




typedef struct
{



  union
  {
    volatile uint32_t ctrl1;
    struct
    {
      volatile uint32_t tmren : 1;
      volatile uint32_t ovfen : 1;
      volatile uint32_t ovfs : 1;
      volatile uint32_t ocmen : 1;
      volatile uint32_t cnt_dir : 3;
      volatile uint32_t prben : 1;
      volatile uint32_t clkdiv : 2;
      volatile uint32_t pmen : 1;
      volatile uint32_t reserved1 : 21;
    } ctrl1_bit;
  };




  union
  {
    volatile uint32_t ctrl2;
    struct
    {
      volatile uint32_t cbctrl : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t ccfs : 1;
      volatile uint32_t drs : 1;
      volatile uint32_t ptos : 3;
      volatile uint32_t c1insel : 1;
      volatile uint32_t c1ios : 1;
      volatile uint32_t c1cios : 1;
      volatile uint32_t c2ios : 1;
      volatile uint32_t c2cios : 1;
      volatile uint32_t c3ios : 1;
      volatile uint32_t c3cios : 1;
      volatile uint32_t c4ios : 1;
      volatile uint32_t reserved2 : 16;
      volatile uint32_t trgout2en : 1;
    } ctrl2_bit;
  };




  union
  {
    volatile uint32_t stctrl;
    struct
    {
      volatile uint32_t smsel : 3;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t stis : 3;
      volatile uint32_t sts : 1;
      volatile uint32_t esf : 4;
      volatile uint32_t esdiv : 2;
      volatile uint32_t ecmben : 1;
      volatile uint32_t esp : 1;
      volatile uint32_t reserved2 : 16;
    } stctrl_bit;
  };




  union
  {
    volatile uint32_t iden;
    struct
    {
      volatile uint32_t ovfien : 1;
      volatile uint32_t c1ien : 1;
      volatile uint32_t c2ien : 1;
      volatile uint32_t c3ien : 1;
      volatile uint32_t c4ien : 1;
      volatile uint32_t hallien : 1;
      volatile uint32_t tien : 1;
      volatile uint32_t brkie : 1;
      volatile uint32_t ovfden : 1;
      volatile uint32_t c1den : 1;
      volatile uint32_t c2den : 1;
      volatile uint32_t c3den : 1;
      volatile uint32_t c4den : 1;
      volatile uint32_t hallde : 1;
      volatile uint32_t tden : 1;
      volatile uint32_t reserved1 : 17;
    } iden_bit;
  };




  union
  {
    volatile uint32_t ists;
    struct
    {
      volatile uint32_t ovfif : 1;
      volatile uint32_t c1if : 1;
      volatile uint32_t c2if : 1;
      volatile uint32_t c3if : 1;
      volatile uint32_t c4if : 1;
      volatile uint32_t hallif : 1;
      volatile uint32_t trgif : 1;
      volatile uint32_t brkif : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t c1rf : 1;
      volatile uint32_t c2rf : 1;
      volatile uint32_t c3rf : 1;
      volatile uint32_t c4rf : 1;
      volatile uint32_t reserved2 : 19;
    } ists_bit;
  };




  union
  {
    volatile uint32_t swevt;
    struct
    {
      volatile uint32_t ovfswtr : 1;
      volatile uint32_t c1swtr : 1;
      volatile uint32_t c2swtr : 1;
      volatile uint32_t c3swtr : 1;
      volatile uint32_t c4swtr : 1;
      volatile uint32_t hallswtr : 1;
      volatile uint32_t trgswtr : 1;
      volatile uint32_t brkswtr : 1;
      volatile uint32_t reserved : 24;
    } swevt_bit;
  };




  union
  {
    volatile uint32_t cm1;




    struct
    {
      volatile uint32_t c1c : 2;
      volatile uint32_t c1oien : 1;
      volatile uint32_t c1oben : 1;
      volatile uint32_t c1octrl : 3;
      volatile uint32_t c1osen : 1;
      volatile uint32_t c2c : 2;
      volatile uint32_t c2oien : 1;
      volatile uint32_t c2oben : 1;
      volatile uint32_t c2octrl : 3;
      volatile uint32_t c2osen : 1;
      volatile uint32_t reserved1 : 16;
    } cm1_output_bit;




    struct
    {
      volatile uint32_t c1c : 2;
      volatile uint32_t c1idiv : 2;
      volatile uint32_t c1df : 4;
      volatile uint32_t c2c : 2;
      volatile uint32_t c2idiv : 2;
      volatile uint32_t c2df : 4;
      volatile uint32_t reserved1 : 16;
    } cm1_input_bit;
  };




  union
  {
    volatile uint32_t cm2;




    struct
    {
      volatile uint32_t c3c : 2;
      volatile uint32_t c3oien : 1;
      volatile uint32_t c3oben : 1;
      volatile uint32_t c3octrl : 3;
      volatile uint32_t c3osen : 1;
      volatile uint32_t c4c : 2;
      volatile uint32_t c4oien : 1;
      volatile uint32_t c4oben : 1;
      volatile uint32_t c4octrl : 3;
      volatile uint32_t c4osen : 1;
      volatile uint32_t reserved1 : 16;
    } cm2_output_bit;




    struct
    {
      volatile uint32_t c3c : 2;
      volatile uint32_t c3idiv : 2;
      volatile uint32_t c3df : 4;
      volatile uint32_t c4c : 2;
      volatile uint32_t c4idiv : 2;
      volatile uint32_t c4df : 4;
      volatile uint32_t reserved1 : 16;
    } cm2_input_bit;
  };




  union
  {
    uint32_t cctrl;
    struct
    {
      volatile uint32_t c1en : 1;
      volatile uint32_t c1p : 1;
      volatile uint32_t c1cen : 1;
      volatile uint32_t c1cp : 1;
      volatile uint32_t c2en : 1;
      volatile uint32_t c2p : 1;
      volatile uint32_t c2cen : 1;
      volatile uint32_t c2cp : 1;
      volatile uint32_t c3en : 1;
      volatile uint32_t c3p : 1;
      volatile uint32_t c3cen : 1;
      volatile uint32_t c3cp : 1;
      volatile uint32_t c4en : 1;
      volatile uint32_t c4p : 1;
      volatile uint32_t reserved1 : 18;
    } cctrl_bit;
  };




  union
  {
    volatile uint32_t cval;
    struct
    {
      volatile uint32_t cval : 32;
    } cval_bit;
  };




  union
  {
    volatile uint32_t div;
    struct
    {
      volatile uint32_t div : 16;
      volatile uint32_t reserved1 : 16;
    } div_bit;
  };




  union
  {
    volatile uint32_t pr;
    struct
    {
      volatile uint32_t pr : 32;
    } pr_bit;
  };




  union
  {
    volatile uint32_t rpr;
    struct
    {
      volatile uint32_t rpr : 16;
      volatile uint32_t reserved1 : 16;
    } rpr_bit;
  };




  union
  {
    uint32_t c1dt;
    struct
    {
      volatile uint32_t c1dt : 32;
    } c1dt_bit;
  };




  union
  {
    uint32_t c2dt;
    struct
    {
      volatile uint32_t c2dt : 32;
    } c2dt_bit;
  };




  union
  {
    volatile uint32_t c3dt;
    struct
    {
      volatile uint32_t c3dt : 32;
    } c3dt_bit;
  };




  union
  {
    volatile uint32_t c4dt;
    struct
    {
      volatile uint32_t c4dt : 32;
    } c4dt_bit;
  };




  union
  {
    volatile uint32_t brk;
    struct
    {
      volatile uint32_t dtc : 8;
      volatile uint32_t wpc : 2;
      volatile uint32_t fcsodis : 1;
      volatile uint32_t fcsoen : 1;
      volatile uint32_t brken : 1;
      volatile uint32_t brkv : 1;
      volatile uint32_t aoen : 1;
      volatile uint32_t oen : 1;
      volatile uint32_t reserved1 : 16;
    } brk_bit;
  };



  union
  {
    volatile uint32_t dmactrl;
    struct
    {
      volatile uint32_t addr : 5;
      volatile uint32_t reserved1 : 3;
      volatile uint32_t dtb : 5;
      volatile uint32_t reserved2 : 19;
    } dmactrl_bit;
  };




  union
  {
    volatile uint32_t dmadt;
    struct
    {
      volatile uint32_t dmadt : 16;
      volatile uint32_t reserved1 : 16;
    } dmadt_bit;
  };




  union
  {
    volatile uint32_t rmp;
    struct
    {
      volatile uint32_t reserved1 : 6;
      volatile uint32_t tmr5_ch4_irmp : 2;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t tmr2_ch1_irmp : 2;
      volatile uint32_t reserved3 : 20;
    } rmp_bit;
  };




  volatile uint32_t reserved1[7];




  union
  {
    volatile uint32_t cm3;
    struct
    {
      volatile uint32_t reserved1 : 2;
      volatile uint32_t c5oien : 1;
      volatile uint32_t c5oben : 1;
      volatile uint32_t c5octrl : 3;
      volatile uint32_t c5osen : 1;
      volatile uint32_t reserved2 : 24;
    } cm3_output_bit;
  };




  union
  {
    volatile uint32_t c5dt;
    struct
    {
      volatile uint32_t c5dt : 32;
    } c5dt_bit;
  };
} tmr_type;
# 915 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_tmr.h"
void tmr_reset(tmr_type *tmr_x);
void tmr_counter_enable(tmr_type *tmr_x, confirm_state new_state);
void tmr_output_default_para_init(tmr_output_config_type *tmr_output_struct);
void tmr_input_default_para_init(tmr_input_config_type *tmr_input_struct);
void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct);
void tmr_base_init(tmr_type* tmr_x, uint32_t tmr_pr, uint32_t tmr_div);
void tmr_clock_source_div_set(tmr_type *tmr_x, tmr_clock_division_type tmr_clock_div);
void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir);
void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value);
void tmr_counter_value_set(tmr_type *tmr_x, uint32_t tmr_cnt_value);
uint32_t tmr_counter_value_get(tmr_type *tmr_x);
void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value);
uint32_t tmr_div_value_get(tmr_type *tmr_x);
void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, tmr_output_config_type *tmr_output_struct);

void tmr_output_channel_mode_select(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, tmr_output_control_mode_type oc_mode);

void tmr_period_value_set(tmr_type *tmr_x, uint32_t tmr_pr_value);
uint32_t tmr_period_value_get(tmr_type *tmr_x);
void tmr_channel_value_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, uint32_t tmr_channel_value);

uint32_t tmr_channel_value_get(tmr_type *tmr_x, tmr_channel_select_type tmr_channel);
void tmr_period_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
void tmr_output_channel_buffer_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, confirm_state new_state);

void tmr_output_channel_immediately_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, confirm_state new_state);

void tmr_output_channel_switch_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, confirm_state new_state);

void tmr_one_cycle_mode_enable(tmr_type *tmr_x, confirm_state new_state);
void tmr_32_bit_function_enable (tmr_type *tmr_x, confirm_state new_state);
void tmr_overflow_request_source_set(tmr_type *tmr_x, confirm_state new_state);
void tmr_overflow_event_disable(tmr_type *tmr_x, confirm_state new_state);
void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct, tmr_channel_input_divider_type divider_factor);

void tmr_channel_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, confirm_state new_state);
void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, uint16_t filter_value);

void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, tmr_channel_input_divider_type divider_factor);

void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect);
void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, tmr_channel_input_divider_type divider_factor);

void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode);
void tmr_sub_mode_select(tmr_type *tmr_x, tmr_sub_mode_select_type sub_mode);
void tmr_channel_dma_select(tmr_type *tmr_x, tmr_dma_request_source_type cc_dma_select);
void tmr_hall_select(tmr_type *tmr_x, confirm_state new_state);
void tmr_channel_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
void tmr_trgout2_enable(tmr_type *tmr_x, confirm_state new_state);
void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_select);
void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state);
void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state);
void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state);
flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag);
void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event);
void tmr_output_enable(tmr_type *tmr_x, confirm_state new_state);
void tmr_internal_clock_set(tmr_type *tmr_x);
void tmr_output_channel_polarity_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, tmr_polarity_active_type oc_polarity);

void tmr_external_clock_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);

void tmr_external_clock_mode1_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);

void tmr_external_clock_mode2_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);

void tmr_encoder_mode_config(tmr_type *tmr_x, tmr_encoder_mode_type encoder_mode, tmr_input_polarity_type ic1_polarity, tmr_input_polarity_type ic2_polarity);

void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, tmr_force_output_type force_output);

void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, tmr_dma_address_type dma_base_address);

void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct);
void tmr_iremap_config(tmr_type *tmr_x, tmr_input_remap_type input_remap);
# 88 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_ertc.h" 1
# 114 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_ertc.h"
typedef enum
{
  ERTC_HOUR_MODE_24 = 0x00,
  ERTC_HOUR_MODE_12 = 0x01
} ertc_hour_mode_set_type;




typedef enum
{
  ERTC_24H = 0x00,
  ERTC_AM = 0x00,
  ERTC_PM = 0x01
} ertc_am_pm_type;




typedef enum
{
  ERTC_SLECT_DATE = 0x00,
  ERTC_SLECT_WEEK = 0x01
} ertc_week_date_select_type;




typedef enum
{
  ERTC_ALA = 0x00,
  ERTC_ALB = 0x01
} ertc_alarm_type;




typedef enum
{
  ERTC_ALARM_SBS_MASK_ALL = 0x00,
  ERTC_ALARM_SBS_MASK_14_1 = 0x01,
  ERTC_ALARM_SBS_MASK_14_2 = 0x02,
  ERTC_ALARM_SBS_MASK_14_3 = 0x03,
  ERTC_ALARM_SBS_MASK_14_4 = 0x04,
  ERTC_ALARM_SBS_MASK_14_5 = 0x05,
  ERTC_ALARM_SBS_MASK_14_6 = 0x06,
  ERTC_ALARM_SBS_MASK_14_7 = 0x07,
  ERTC_ALARM_SBS_MASK_14_8 = 0x08,
  ERTC_ALARM_SBS_MASK_14_9 = 0x09,
  ERTC_ALARM_SBS_MASK_14_10 = 0x0A,
  ERTC_ALARM_SBS_MASK_14_11 = 0x0B,
  ERTC_ALARM_SBS_MASK_14_12 = 0x0C,
  ERTC_ALARM_SBS_MASK_14_13 = 0x0D,
  ERTC_ALARM_SBS_MASK_14 = 0x0E,
  ERTC_ALARM_SBS_MASK_NONE = 0x0F
} ertc_alarm_sbs_mask_type;




typedef enum
{
  ERTC_WAT_CLK_ERTCCLK_DIV16 = 0x00,
  ERTC_WAT_CLK_ERTCCLK_DIV8 = 0x01,
  ERTC_WAT_CLK_ERTCCLK_DIV4 = 0x02,
  ERTC_WAT_CLK_ERTCCLK_DIV2 = 0x03,
  ERTC_WAT_CLK_CK_B_16BITS = 0x04,
  ERTC_WAT_CLK_CK_B_17BITS = 0x06
} ertc_wakeup_clock_type;




typedef enum
{
  ERTC_SMOOTH_CAL_PERIOD_32 = 0x00,
  ERTC_SMOOTH_CAL_PERIOD_16 = 0x01,
  ERTC_SMOOTH_CAL_PERIOD_8 = 0x02
} ertc_smooth_cal_period_type;




typedef enum
{
  ERTC_SMOOTH_CAL_CLK_ADD_0 = 0x00,
  ERTC_SMOOTH_CAL_CLK_ADD_512 = 0x01
} ertc_smooth_cal_clk_add_type;




typedef enum
{
  ERTC_CAL_DIR_POSITIVE = 0x00,
  ERTC_CAL_DIR_NEGATIVE = 0x01
} ertc_cal_direction_type;




typedef enum
{
  ERTC_CAL_OUTPUT_512HZ = 0x00,
  ERTC_CAL_OUTPUT_1HZ = 0x01
} ertc_cal_output_select_type;




typedef enum
{
  ERTC_TIME_ADD_NONE = 0x00,
  ERTC_TIME_ADD_1S = 0x01
} ertc_time_adjust_type;




typedef enum
{
  ERTC_DST_ADD_1H = 0x00,
  ERTC_DST_DEC_1H = 0x01
} ertc_dst_operation_type;




typedef enum
{
  ERTC_DST_SAVE_0 = 0x00,
  ERTC_DST_SAVE_1 = 0x01
} ertc_dst_save_type;




typedef enum
{
  ERTC_OUTPUT_DISABLE = 0x00,
  ERTC_OUTPUT_ALARM_A = 0x01,
  ERTC_OUTPUT_ALARM_B = 0x02,
  ERTC_OUTPUT_WAKEUP = 0x03
} ertc_output_source_type;




typedef enum
{
  ERTC_OUTPUT_POLARITY_HIGH = 0x00,
  ERTC_OUTPUT_POLARITY_LOW = 0x01
} ertc_output_polarity_type;




typedef enum
{
  ERTC_OUTPUT_TYPE_OPEN_DRAIN = 0x00,
  ERTC_OUTPUT_TYPE_PUSH_PULL = 0x01
} ertc_output_type;




typedef enum
{
  ERTC_PIN_PC13 = 0x00,
  ERTC_PIN_PA0 = 0x01
} ertc_pin_select_type;




typedef enum
{
  ERTC_TIMESTAMP_EDGE_RISING = 0x00,
  ERTC_TIMESTAMP_EDGE_FALLING = 0x01
} ertc_timestamp_valid_edge_type;




typedef enum
{
  ERTC_TAMPER_1 = 0x00,
  ERTC_TAMPER_2 = 0x01
} ertc_tamper_select_type;




typedef enum
{
  ERTC_TAMPER_PR_1_ERTCCLK = 0x00,
  ERTC_TAMPER_PR_2_ERTCCLK = 0x01,
  ERTC_TAMPER_PR_4_ERTCCLK = 0x02,
  ERTC_TAMPER_PR_8_ERTCCLK = 0x03
} ertc_tamper_precharge_type;




typedef enum
{
  ERTC_TAMPER_FILTER_DISABLE = 0x00,
  ERTC_TAMPER_FILTER_2 = 0x01,
  ERTC_TAMPER_FILTER_4 = 0x02,
  ERTC_TAMPER_FILTER_8 = 0x03
} ertc_tamper_filter_type;




typedef enum
{
  ERTC_TAMPER_FREQ_DIV_32768 = 0x00,
  ERTC_TAMPER_FREQ_DIV_16384 = 0x01,
  ERTC_TAMPER_FREQ_DIV_8192 = 0x02,
  ERTC_TAMPER_FREQ_DIV_4096 = 0x03,
  ERTC_TAMPER_FREQ_DIV_2048 = 0x04,
  ERTC_TAMPER_FREQ_DIV_1024 = 0x05,
  ERTC_TAMPER_FREQ_DIV_512 = 0x06,
  ERTC_TAMPER_FREQ_DIV_256 = 0x07
} ertc_tamper_detect_freq_type;




typedef enum
{
  ERTC_TAMPER_EDGE_RISING = 0x00,
  ERTC_TAMPER_EDGE_FALLING = 0x01,
  ERTC_TAMPER_EDGE_LOW = 0x00,
  ERTC_TAMPER_EDGE_HIGH = 0x01
} ertc_tamper_valid_edge_type;




typedef enum
{
  ERTC_DT1 = 0,
  ERTC_DT2 = 1,
  ERTC_DT3 = 2,
  ERTC_DT4 = 3,
  ERTC_DT5 = 4,
  ERTC_DT6 = 5,
  ERTC_DT7 = 6,
  ERTC_DT8 = 7,
  ERTC_DT9 = 8,
  ERTC_DT10 = 9,
  ERTC_DT11 = 10,
  ERTC_DT12 = 11,
  ERTC_DT13 = 12,
  ERTC_DT14 = 13,
  ERTC_DT15 = 14,
  ERTC_DT16 = 15,
  ERTC_DT17 = 16,
  ERTC_DT18 = 17,
  ERTC_DT19 = 18,
  ERTC_DT20 = 19
} ertc_dt_type;




typedef struct
{
  uint8_t year;
  uint8_t month;
  uint8_t day;
  uint8_t hour;
  uint8_t min;
  uint8_t sec;
  uint8_t week;
  ertc_am_pm_type ampm;
} ertc_time_type;




typedef struct
{
  uint8_t day;
  uint8_t hour;
  uint8_t min;
  uint8_t sec;
  ertc_am_pm_type ampm;
  uint32_t mask;
  uint8_t week_date_sel;
  uint8_t week;
} ertc_alarm_value_type;




typedef union
{
  volatile uint32_t time;
  struct
  {
    volatile uint32_t s : 7;
    volatile uint32_t reserved1 : 1;
    volatile uint32_t m : 7;
    volatile uint32_t reserved2 : 1;
    volatile uint32_t h : 6;
    volatile uint32_t ampm : 1;
    volatile uint32_t reserved3 : 9;
  } time_bit;
} ertc_reg_time_type;




typedef union
{
  volatile uint32_t date;
  struct
  {
    volatile uint32_t d :6;
    volatile uint32_t reserved1 :2;
    volatile uint32_t m :5;
    volatile uint32_t wk :3;
    volatile uint32_t y :8;
    volatile uint32_t reserved2 :8;
  } date_bit;
} ertc_reg_date_type;




typedef union
{
  volatile uint32_t ala;
  struct
  {
    volatile uint32_t s :7;
    volatile uint32_t mask1 :1;
    volatile uint32_t m :7;
    volatile uint32_t mask2 :1;
    volatile uint32_t h :6;
    volatile uint32_t ampm :1;
    volatile uint32_t mask3 :1;
    volatile uint32_t d :6;
    volatile uint32_t wksel :1;
    volatile uint32_t mask4 :1;
  } ala_bit;
} ertc_reg_alarm_type;




typedef union
{
  volatile uint32_t scal;
  struct
  {
    volatile uint32_t dec :9;
    volatile uint32_t reserved1 :4;
    volatile uint32_t cal16 :1;
    volatile uint32_t cal8 :1;
    volatile uint32_t add :1;
    volatile uint32_t reserved2 :16;
  } scal_bit;
} ertc_reg_scal_type;




typedef union
{
  volatile uint32_t tadj;
  struct
  {
    volatile uint32_t decsbs :15;
    volatile uint32_t reserved1 :16;
    volatile uint32_t add1s :1;
  } tadj_bit;
} ertc_reg_tadj_type;




typedef union
{
  volatile uint32_t tstm;
  struct
  {
    volatile uint32_t s :7;
    volatile uint32_t reserved1 :1;
    volatile uint32_t m :7;
    volatile uint32_t reserved2 :1;
    volatile uint32_t h :6;
    volatile uint32_t ampm :1;
    volatile uint32_t reserved3 :9;
  } tstm_bit;
} ertc_reg_tstm_type;




typedef union
{
  volatile uint32_t tsdt;
  struct
  {
    volatile uint32_t d :6;
    volatile uint32_t reserved1 :2;
    volatile uint32_t m :5;
    volatile uint32_t wk :3;
    volatile uint32_t reserved2 :16;
  } tsdt_bit;
} ertc_reg_tsdt_type;




typedef struct
{




  union
  {
    volatile uint32_t time;
    struct
    {
      volatile uint32_t s : 7;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t m : 7;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t h : 6;
      volatile uint32_t ampm : 1;
      volatile uint32_t reserved3 : 9;
    } time_bit;
  };




  union
  {
    volatile uint32_t date;
    struct
    {
      volatile uint32_t d :6;
      volatile uint32_t reserved1 :2;
      volatile uint32_t m :5;
      volatile uint32_t wk :3;
      volatile uint32_t y :8;
      volatile uint32_t reserved2 :8;
    } date_bit;
  };




  union
  {
    volatile uint32_t ctrl;
    struct
    {
      volatile uint32_t watclk :3;
      volatile uint32_t tsedg :1;
      volatile uint32_t rcden :1;
      volatile uint32_t dren :1;
      volatile uint32_t hm :1;
      volatile uint32_t ccalen :1;
      volatile uint32_t alaen :1;
      volatile uint32_t alben :1;
      volatile uint32_t waten :1;
      volatile uint32_t tsen :1;
      volatile uint32_t alaien :1;
      volatile uint32_t albien :1;
      volatile uint32_t watien :1;
      volatile uint32_t tsien :1;
      volatile uint32_t add1h :1;
      volatile uint32_t dec1h :1;
      volatile uint32_t bpr :1;
      volatile uint32_t calosel :1;
      volatile uint32_t outp :1;
      volatile uint32_t outsel :2;
      volatile uint32_t caloen :1;
      volatile uint32_t reserved1 :8;
    } ctrl_bit;
  };




  union
  {
    volatile uint32_t sts;
    struct
    {
      volatile uint32_t alawf :1;
      volatile uint32_t albwf :1;
      volatile uint32_t watwf :1;
      volatile uint32_t tadjf :1;
      volatile uint32_t initf :1;
      volatile uint32_t updf :1;
      volatile uint32_t imf :1;
      volatile uint32_t imen :1;
      volatile uint32_t alaf :1;
      volatile uint32_t albf :1;
      volatile uint32_t watf :1;
      volatile uint32_t tsf :1;
      volatile uint32_t tsof :1;
      volatile uint32_t tp1f :1;
      volatile uint32_t tp2f :1;
      volatile uint32_t reserved1 :1;
      volatile uint32_t calupdf :1;
      volatile uint32_t reserved2 :15;
    } sts_bit;
  };




  union
  {
    volatile uint32_t div;
    struct
    {
      volatile uint32_t divb :15;
      volatile uint32_t reserved1 :1;
      volatile uint32_t diva :7;
      volatile uint32_t reserved2 :9;
    } div_bit;
  };




  union
  {
    volatile uint32_t wat;
    struct
    {
      volatile uint32_t val :16;
      volatile uint32_t reserved1 :16;
    } wat_bit;
  };




  union
  {
    volatile uint32_t ccal;
    struct
    {
      volatile uint32_t calval :5;
      volatile uint32_t reserved1 :2;
      volatile uint32_t caldir :1;
      volatile uint32_t reserved2 :24;
    } ccal_bit;
  };




  union
  {
    volatile uint32_t ala;
    struct
    {
      volatile uint32_t s :7;
      volatile uint32_t mask1 :1;
      volatile uint32_t m :7;
      volatile uint32_t mask2 :1;
      volatile uint32_t h :6;
      volatile uint32_t ampm :1;
      volatile uint32_t mask3 :1;
      volatile uint32_t d :6;
      volatile uint32_t wksel :1;
      volatile uint32_t mask4 :1;
    } ala_bit;
  };




  union
  {
    volatile uint32_t alb;
    struct
    {
      volatile uint32_t s :7;
      volatile uint32_t mask1 :1;
      volatile uint32_t m :7;
      volatile uint32_t mask2 :1;
      volatile uint32_t h :6;
      volatile uint32_t ampm :1;
      volatile uint32_t mask3 :1;
      volatile uint32_t d :6;
      volatile uint32_t wksel :1;
      volatile uint32_t mask4 :1;
    } alb_bit;
  };




  union
  {
    volatile uint32_t wp;
    struct
    {
      volatile uint32_t cmd :8;
      volatile uint32_t reserved1 :24;
    } wp_bit;
  };




  union
  {
    volatile uint32_t sbs;
    struct
    {
      volatile uint32_t sbs :16;
      volatile uint32_t reserved1 :16;
    } sbs_bit;
  };




  union
  {
    volatile uint32_t tadj;
    struct
    {
      volatile uint32_t decsbs :15;
      volatile uint32_t reserved1 :16;
      volatile uint32_t add1s :1;
    } tadj_bit;
  };




  union
  {
    volatile uint32_t tstm;
    struct
    {
      volatile uint32_t s :7;
      volatile uint32_t reserved1 :1;
      volatile uint32_t m :7;
      volatile uint32_t reserved2 :1;
      volatile uint32_t h :6;
      volatile uint32_t ampm :1;
      volatile uint32_t reserved3 :9;
    } tstm_bit;
  };




  union
  {
    volatile uint32_t tsdt;
    struct
    {
      volatile uint32_t d :6;
      volatile uint32_t reserved1 :2;
      volatile uint32_t m :5;
      volatile uint32_t wk :3;
      volatile uint32_t reserved2 :16;
    } tsdt_bit;
  };




  union
  {
    volatile uint32_t tssbs;
    struct
    {
      volatile uint32_t sbs :16;
      volatile uint32_t reserved1 :16;
    } tssbs_bit;
  };




  union
  {
    volatile uint32_t scal;
    struct
    {
      volatile uint32_t dec :9;
      volatile uint32_t reserved1 :4;
      volatile uint32_t cal16 :1;
      volatile uint32_t cal8 :1;
      volatile uint32_t add :1;
      volatile uint32_t reserved2 :16;
    } scal_bit;
  };




  union
  {
    volatile uint32_t tamp;
    struct
    {
      volatile uint32_t tp1en :1;
      volatile uint32_t tp1edg :1;
      volatile uint32_t tpien :1;
      volatile uint32_t tp2en :1;
      volatile uint32_t tp2edg :1;
      volatile uint32_t reserved1 :2;
      volatile uint32_t tptsen :1;
      volatile uint32_t tpfreq :3;
      volatile uint32_t tpflt :2;
      volatile uint32_t tppr :2;
      volatile uint32_t tppu :1;
      volatile uint32_t tp1pin :1;
      volatile uint32_t tspin :1;
      volatile uint32_t outtype :1;
      volatile uint32_t reserved2 :13;
    } tamp_bit;
  };




  union
  {
    volatile uint32_t alasbs;
    struct
    {
      volatile uint32_t sbs :15;
      volatile uint32_t reserved1 :9;
      volatile uint32_t sbsmsk :4;
      volatile uint32_t reserved2 :4;
    } alasbs_bit;
  };




  union
  {
    volatile uint32_t albsbs;
    struct
    {
      volatile uint32_t sbs :15;
      volatile uint32_t reserved1 :9;
      volatile uint32_t sbsmsk :4;
      volatile uint32_t reserved2 :4;
    } albsbs_bit;
  };




  volatile uint32_t reserved1;




  union
  {
    volatile uint32_t dt1;
    struct
    {
      volatile uint32_t dt :32;
    } dt1_bit;
  };




  union
  {
    volatile uint32_t dt2;
    struct
    {
      volatile uint32_t dt :32;
    } dt2_bit;
  };




  union
  {
    volatile uint32_t dt3;
    struct
    {
      volatile uint32_t dt :32;
    } dt3_bit;
  };




  union
  {
    volatile uint32_t dt4;
    struct
    {
      volatile uint32_t dt :32;
    } dt4_bit;
  };




  union
  {
    volatile uint32_t dt5;
    struct
    {
      volatile uint32_t dt :32;
    } dt5_bit;
  };




  union
  {
    volatile uint32_t dt6;
    struct
    {
      volatile uint32_t dt :32;
    } dt6_bit;
  };




  union
  {
    volatile uint32_t dt7;
    struct
    {
      volatile uint32_t dt :32;
    } dt7_bit;
  };




  union
  {
    volatile uint32_t dt8;
    struct
    {
      volatile uint32_t dt :32;
    } dt8_bit;
  };




  union
  {
    volatile uint32_t dt9;
    struct
    {
      volatile uint32_t dt :32;
    } dt9_bit;
  };




  union
  {
    volatile uint32_t dt10;
    struct
    {
      volatile uint32_t dt :32;
    } dt10_bit;
  };




  union
  {
    volatile uint32_t dt11;
    struct
    {
      volatile uint32_t dt :32;
    } dt11_bit;
  };




  union
  {
    volatile uint32_t dt12;
    struct
    {
      volatile uint32_t dt :32;
    } dt12_bit;
  };




  union
  {
    volatile uint32_t dt13;
    struct
    {
      volatile uint32_t dt :32;
    } dt13_bit;
  };




  union
  {
    volatile uint32_t dt14;
    struct
    {
      volatile uint32_t dt :32;
    } dt14_bit;
  };




  union
  {
    volatile uint32_t dt15;
    struct
    {
      volatile uint32_t dt :32;
    } dt15_bit;
  };




  union
  {
    volatile uint32_t dt16;
    struct
    {
      volatile uint32_t dt :32;
    } dt16_bit;
  };




  union
  {
    volatile uint32_t dt17;
    struct
    {
      volatile uint32_t dt :32;
    } dt17_bit;
  };




  union
  {
    volatile uint32_t dt18;
    struct
    {
      volatile uint32_t dt :32;
    } dt18_bit;
  };




  union
  {
    volatile uint32_t dt19;
    struct
    {
      volatile uint32_t dt :32;
    } dt19_bit;
  };




  union
  {
    volatile uint32_t dt20;
    struct
    {
      volatile uint32_t dt :32;
    } dt20_bit;
  };


} ertc_type;
# 1136 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_ertc.h"
uint8_t ertc_num_to_bcd(uint8_t num);
uint8_t ertc_bcd_to_num(uint8_t bcd);
void ertc_write_protect_enable(void);
void ertc_write_protect_disable(void);
error_status ertc_wait_update(void);
error_status ertc_wait_flag(uint32_t flag, flag_status status);
error_status ertc_init_mode_enter(void);
void ertc_init_mode_exit(void);
error_status ertc_reset(void);
error_status ertc_divider_set(uint16_t div_a, uint16_t div_b);
error_status ertc_hour_mode_set(ertc_hour_mode_set_type mode);
error_status ertc_date_set(uint8_t year, uint8_t month, uint8_t date, uint8_t week);
error_status ertc_time_set(uint8_t hour, uint8_t min, uint8_t sec, ertc_am_pm_type ampm);
void ertc_calendar_get(ertc_time_type* time);
uint32_t ertc_sub_second_get(void);
void ertc_alarm_mask_set(ertc_alarm_type alarm_x, uint32_t mask);
void ertc_alarm_week_date_select(ertc_alarm_type alarm_x, ertc_week_date_select_type wk);
void ertc_alarm_set(ertc_alarm_type alarm_x, uint8_t week_date, uint8_t hour, uint8_t min, uint8_t sec, ertc_am_pm_type ampm);
void ertc_alarm_sub_second_set(ertc_alarm_type alarm_x, uint32_t value, ertc_alarm_sbs_mask_type mask);
error_status ertc_alarm_enable(ertc_alarm_type alarm_x, confirm_state new_state);
void ertc_alarm_get(ertc_alarm_type alarm_x, ertc_alarm_value_type* alarm);
uint32_t ertc_alarm_sub_second_get(ertc_alarm_type alarm_x);
void ertc_wakeup_clock_set(ertc_wakeup_clock_type clock);
void ertc_wakeup_counter_set(uint32_t counter);
uint16_t ertc_wakeup_counter_get(void);
error_status ertc_wakeup_enable(confirm_state new_state);
error_status ertc_smooth_calibration_config(ertc_smooth_cal_period_type period, ertc_smooth_cal_clk_add_type clk_add, uint32_t clk_dec);
error_status ertc_coarse_calibration_set(ertc_cal_direction_type dir, uint32_t value);
error_status ertc_coarse_calibration_enable(confirm_state new_state);
void ertc_cal_output_select(ertc_cal_output_select_type output);
void ertc_cal_output_enable(confirm_state new_state);
error_status ertc_time_adjust(ertc_time_adjust_type add1s, uint32_t decsbs);
void ertc_daylight_set(ertc_dst_operation_type operation, ertc_dst_save_type save);
uint8_t ertc_daylight_bpr_get(void);
error_status ertc_refer_clock_detect_enable(confirm_state new_state);
void ertc_direct_read_enable(confirm_state new_state);
void ertc_output_set(ertc_output_source_type source, ertc_output_polarity_type polarity, ertc_output_type type);
void ertc_timestamp_pin_select(ertc_pin_select_type pin);
void ertc_timestamp_valid_edge_set(ertc_timestamp_valid_edge_type edge);
void ertc_timestamp_enable(confirm_state new_state);
void ertc_timestamp_get(ertc_time_type* time);
uint32_t ertc_timestamp_sub_second_get(void);
void ertc_tamper_1_pin_select(ertc_pin_select_type pin);
void ertc_tamper_pull_up_enable(confirm_state new_state);
void ertc_tamper_precharge_set(ertc_tamper_precharge_type precharge);
void ertc_tamper_filter_set(ertc_tamper_filter_type filter);
void ertc_tamper_detect_freq_set(ertc_tamper_detect_freq_type freq);
void ertc_tamper_valid_edge_set(ertc_tamper_select_type tamper_x, ertc_tamper_valid_edge_type trigger);
void ertc_tamper_timestamp_enable(confirm_state new_state);
void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_state);
void ertc_interrupt_enable(uint32_t source, confirm_state new_state);
flag_status ertc_interrupt_get(uint32_t source);
flag_status ertc_flag_get(uint32_t flag);
void ertc_flag_clear(uint32_t flag);
void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data);
uint32_t ertc_bpr_data_read(ertc_dt_type dt);
# 91 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_gpio.h" 1
# 80 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_gpio.h"
typedef enum
{
  GPIO_MODE_INPUT = 0x00,
  GPIO_MODE_OUTPUT = 0x01,
  GPIO_MODE_MUX = 0x02,
  GPIO_MODE_ANALOG = 0x03
} gpio_mode_type;




typedef enum
{
  GPIO_DRIVE_STRENGTH_STRONGER = 0x01,
  GPIO_DRIVE_STRENGTH_MODERATE = 0x02
} gpio_drive_type;




typedef enum
{
  GPIO_OUTPUT_PUSH_PULL = 0x00,
  GPIO_OUTPUT_OPEN_DRAIN = 0x01
} gpio_output_type;




typedef enum
{
  GPIO_PULL_NONE = 0x00,
  GPIO_PULL_UP = 0x01,
  GPIO_PULL_DOWN = 0x02
} gpio_pull_type;




typedef struct
{
  uint32_t gpio_pins;
  gpio_output_type gpio_out_type;
  gpio_pull_type gpio_pull;
  gpio_mode_type gpio_mode;
  gpio_drive_type gpio_drive_strength;
} gpio_init_type;




typedef enum
{
  GPIO_PINS_SOURCE0 = 0x00,
  GPIO_PINS_SOURCE1 = 0x01,
  GPIO_PINS_SOURCE2 = 0x02,
  GPIO_PINS_SOURCE3 = 0x03,
  GPIO_PINS_SOURCE4 = 0x04,
  GPIO_PINS_SOURCE5 = 0x05,
  GPIO_PINS_SOURCE6 = 0x06,
  GPIO_PINS_SOURCE7 = 0x07,
  GPIO_PINS_SOURCE8 = 0x08,
  GPIO_PINS_SOURCE9 = 0x09,
  GPIO_PINS_SOURCE10 = 0x0A,
  GPIO_PINS_SOURCE11 = 0x0B,
  GPIO_PINS_SOURCE12 = 0x0C,
  GPIO_PINS_SOURCE13 = 0x0D,
  GPIO_PINS_SOURCE14 = 0x0E,
  GPIO_PINS_SOURCE15 = 0x0F
} gpio_pins_source_type;




typedef enum
{
  GPIO_MUX_0 = 0x00,
  GPIO_MUX_1 = 0x01,
  GPIO_MUX_2 = 0x02,
  GPIO_MUX_3 = 0x03,
  GPIO_MUX_4 = 0x04,
  GPIO_MUX_5 = 0x05,
  GPIO_MUX_6 = 0x06,
  GPIO_MUX_7 = 0x07,
  GPIO_MUX_8 = 0x08,
  GPIO_MUX_9 = 0x09,
  GPIO_MUX_10 = 0x0A,
  GPIO_MUX_11 = 0x0B,
  GPIO_MUX_12 = 0x0C,
  GPIO_MUX_13 = 0x0D,
  GPIO_MUX_14 = 0x0E,
  GPIO_MUX_15 = 0x0F
} gpio_mux_sel_type;




typedef struct
{



  union
  {
    volatile uint32_t cfgr;
    struct
    {
      volatile uint32_t iomc0 : 2;
      volatile uint32_t iomc1 : 2;
      volatile uint32_t iomc2 : 2;
      volatile uint32_t iomc3 : 2;
      volatile uint32_t iomc4 : 2;
      volatile uint32_t iomc5 : 2;
      volatile uint32_t iomc6 : 2;
      volatile uint32_t iomc7 : 2;
      volatile uint32_t iomc8 : 2;
      volatile uint32_t iomc9 : 2;
      volatile uint32_t iomc10 : 2;
      volatile uint32_t iomc11 : 2;
      volatile uint32_t iomc12 : 2;
      volatile uint32_t iomc13 : 2;
      volatile uint32_t iomc14 : 2;
      volatile uint32_t iomc15 : 2;
    } cfgr_bit;
  };




  union
  {
    volatile uint32_t omode;
    struct
    {
      volatile uint32_t om0 : 1;
      volatile uint32_t om1 : 1;
      volatile uint32_t om2 : 1;
      volatile uint32_t om3 : 1;
      volatile uint32_t om4 : 1;
      volatile uint32_t om5 : 1;
      volatile uint32_t om6 : 1;
      volatile uint32_t om7 : 1;
      volatile uint32_t om8 : 1;
      volatile uint32_t om9 : 1;
      volatile uint32_t om10 : 1;
      volatile uint32_t om11 : 1;
      volatile uint32_t om12 : 1;
      volatile uint32_t om13 : 1;
      volatile uint32_t om14 : 1;
      volatile uint32_t om15 : 1;
      volatile uint32_t reserved1 : 16;
    } omode_bit;
  };




  union
  {
    volatile uint32_t odrvr;
    struct
    {
      volatile uint32_t odrv0 : 2;
      volatile uint32_t odrv1 : 2;
      volatile uint32_t odrv2 : 2;
      volatile uint32_t odrv3 : 2;
      volatile uint32_t odrv4 : 2;
      volatile uint32_t odrv5 : 2;
      volatile uint32_t odrv6 : 2;
      volatile uint32_t odrv7 : 2;
      volatile uint32_t odrv8 : 2;
      volatile uint32_t odrv9 : 2;
      volatile uint32_t odrv10 : 2;
      volatile uint32_t odrv11 : 2;
      volatile uint32_t odrv12 : 2;
      volatile uint32_t odrv13 : 2;
      volatile uint32_t odrv14 : 2;
      volatile uint32_t odrv15 : 2;
    } odrvr_bit;
  };




  union
  {
    volatile uint32_t pull;
    struct
    {
      volatile uint32_t pull0 : 2;
      volatile uint32_t pull1 : 2;
      volatile uint32_t pull2 : 2;
      volatile uint32_t pull3 : 2;
      volatile uint32_t pull4 : 2;
      volatile uint32_t pull5 : 2;
      volatile uint32_t pull6 : 2;
      volatile uint32_t pull7 : 2;
      volatile uint32_t pull8 : 2;
      volatile uint32_t pull9 : 2;
      volatile uint32_t pull10 : 2;
      volatile uint32_t pull11 : 2;
      volatile uint32_t pull12 : 2;
      volatile uint32_t pull13 : 2;
      volatile uint32_t pull14 : 2;
      volatile uint32_t pull15 : 2;
    } pull_bit;
  };




  union
  {
    volatile uint32_t idt;
    struct
    {
      volatile uint32_t idt0 : 1;
      volatile uint32_t idt1 : 1;
      volatile uint32_t idt2 : 1;
      volatile uint32_t idt3 : 1;
      volatile uint32_t idt4 : 1;
      volatile uint32_t idt5 : 1;
      volatile uint32_t idt6 : 1;
      volatile uint32_t idt7 : 1;
      volatile uint32_t idt8 : 1;
      volatile uint32_t idt9 : 1;
      volatile uint32_t idt10 : 1;
      volatile uint32_t idt11 : 1;
      volatile uint32_t idt12 : 1;
      volatile uint32_t idt13 : 1;
      volatile uint32_t idt14 : 1;
      volatile uint32_t idt15 : 1;
      volatile uint32_t reserved1 : 16;
    } idt_bit;
  };




  union
  {
    volatile uint32_t odt;
    struct
    {
      volatile uint32_t odt0 : 1;
      volatile uint32_t odt1 : 1;
      volatile uint32_t odt2 : 1;
      volatile uint32_t odt3 : 1;
      volatile uint32_t odt4 : 1;
      volatile uint32_t odt5 : 1;
      volatile uint32_t odt6 : 1;
      volatile uint32_t odt7 : 1;
      volatile uint32_t odt8 : 1;
      volatile uint32_t odt9 : 1;
      volatile uint32_t odt10 : 1;
      volatile uint32_t odt11 : 1;
      volatile uint32_t odt12 : 1;
      volatile uint32_t odt13 : 1;
      volatile uint32_t odt14 : 1;
      volatile uint32_t odt15 : 1;
      volatile uint32_t reserved1 : 16;
    } odt_bit;
  };




  union
  {
    volatile uint32_t scr;
    struct
    {
      volatile uint32_t iosb0 : 1;
      volatile uint32_t iosb1 : 1;
      volatile uint32_t iosb2 : 1;
      volatile uint32_t iosb3 : 1;
      volatile uint32_t iosb4 : 1;
      volatile uint32_t iosb5 : 1;
      volatile uint32_t iosb6 : 1;
      volatile uint32_t iosb7 : 1;
      volatile uint32_t iosb8 : 1;
      volatile uint32_t iosb9 : 1;
      volatile uint32_t iosb10 : 1;
      volatile uint32_t iosb11 : 1;
      volatile uint32_t iosb12 : 1;
      volatile uint32_t iosb13 : 1;
      volatile uint32_t iosb14 : 1;
      volatile uint32_t iosb15 : 1;
      volatile uint32_t iocb0 : 1;
      volatile uint32_t iocb1 : 1;
      volatile uint32_t iocb2 : 1;
      volatile uint32_t iocb3 : 1;
      volatile uint32_t iocb4 : 1;
      volatile uint32_t iocb5 : 1;
      volatile uint32_t iocb6 : 1;
      volatile uint32_t iocb7 : 1;
      volatile uint32_t iocb8 : 1;
      volatile uint32_t iocb9 : 1;
      volatile uint32_t iocb10 : 1;
      volatile uint32_t iocb11 : 1;
      volatile uint32_t iocb12 : 1;
      volatile uint32_t iocb13 : 1;
      volatile uint32_t iocb14 : 1;
      volatile uint32_t iocb15 : 1;
    } scr_bit;
  };




  union
  {
    volatile uint32_t wpr;
    struct
    {
      volatile uint32_t wpen0 : 1;
      volatile uint32_t wpen1 : 1;
      volatile uint32_t wpen2 : 1;
      volatile uint32_t wpen3 : 1;
      volatile uint32_t wpen4 : 1;
      volatile uint32_t wpen5 : 1;
      volatile uint32_t wpen6 : 1;
      volatile uint32_t wpen7 : 1;
      volatile uint32_t wpen8 : 1;
      volatile uint32_t wpen9 : 1;
      volatile uint32_t wpen10 : 1;
      volatile uint32_t wpen11 : 1;
      volatile uint32_t wpen12 : 1;
      volatile uint32_t wpen13 : 1;
      volatile uint32_t wpen14 : 1;
      volatile uint32_t wpen15 : 1;
      volatile uint32_t wpseq : 1;
      volatile uint32_t reserved1 : 15;
    } wpr_bit;
  };




  union
  {
    volatile uint32_t muxl;
    struct
    {
      volatile uint32_t muxl0 : 4;
      volatile uint32_t muxl1 : 4;
      volatile uint32_t muxl2 : 4;
      volatile uint32_t muxl3 : 4;
      volatile uint32_t muxl4 : 4;
      volatile uint32_t muxl5 : 4;
      volatile uint32_t muxl6 : 4;
      volatile uint32_t muxl7 : 4;
    } muxl_bit;
  };




  union
  {
    volatile uint32_t muxh;
    struct
    {
      volatile uint32_t muxh8 : 4;
      volatile uint32_t muxh9 : 4;
      volatile uint32_t muxh10 : 4;
      volatile uint32_t muxh11 : 4;
      volatile uint32_t muxh12 : 4;
      volatile uint32_t muxh13 : 4;
      volatile uint32_t muxh14 : 4;
      volatile uint32_t muxh15 : 4;
    } muxh_bit;
  };




  union
  {
    volatile uint32_t clr;
    struct
    {
      volatile uint32_t iocb0 : 1;
      volatile uint32_t iocb1 : 1;
      volatile uint32_t iocb2 : 1;
      volatile uint32_t iocb3 : 1;
      volatile uint32_t iocb4 : 1;
      volatile uint32_t iocb5 : 1;
      volatile uint32_t iocb6 : 1;
      volatile uint32_t iocb7 : 1;
      volatile uint32_t iocb8 : 1;
      volatile uint32_t iocb9 : 1;
      volatile uint32_t iocb10 : 1;
      volatile uint32_t iocb11 : 1;
      volatile uint32_t iocb12 : 1;
      volatile uint32_t iocb13 : 1;
      volatile uint32_t iocb14 : 1;
      volatile uint32_t iocb15 : 1;
      volatile uint32_t reserved1 : 16;
    } clr_bit;
  };




  volatile uint32_t reserved1[4];




  union
  {
    volatile uint32_t hdrv;
    struct
    {
      volatile uint32_t hdrv0 : 1;
      volatile uint32_t hdrv1 : 1;
      volatile uint32_t hdrv2 : 1;
      volatile uint32_t hdrv3 : 1;
      volatile uint32_t hdrv4 : 1;
      volatile uint32_t hdrv5 : 1;
      volatile uint32_t hdrv6 : 1;
      volatile uint32_t hdrv7 : 1;
      volatile uint32_t hdrv8 : 1;
      volatile uint32_t hdrv9 : 1;
      volatile uint32_t hdrv10 : 1;
      volatile uint32_t hdrv11 : 1;
      volatile uint32_t hdrv12 : 1;
      volatile uint32_t hdrv13 : 1;
      volatile uint32_t hdrv14 : 1;
      volatile uint32_t hdrv15 : 1;
      volatile uint32_t reserved1 : 16;
    } hdrv_bit;
  };

} gpio_type;
# 534 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_gpio.h"
void gpio_reset(gpio_type *gpio_x);
void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct);
void gpio_default_para_init(gpio_init_type *gpio_init_struct);
flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins);
uint16_t gpio_input_data_read(gpio_type *gpio_x);
flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins);
uint16_t gpio_output_data_read(gpio_type *gpio_x);
void gpio_bits_set(gpio_type *gpio_x, uint16_t pins);
void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins);
void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state);
void gpio_port_write(gpio_type *gpio_x, uint16_t port_value);
void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins);
void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state);
void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_source, gpio_mux_sel_type gpio_mux);
# 94 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_i2c.h" 1
# 102 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_i2c.h"
typedef enum
{
  I2C_SMBUS_MODE_DEVICE = 0x00,
  I2C_SMBUS_MODE_HOST = 0x01
} i2c_smbus_mode_type;




typedef enum
{
  I2C_ADDRESS_MODE_7BIT = 0x00,
  I2C_ADDRESS_MODE_10BIT = 0x01
} i2c_address_mode_type;




typedef enum
{
  I2C_DIR_TRANSMIT = 0x00,
  I2C_DIR_RECEIVE = 0x01
} i2c_transfer_dir_type;




typedef enum
{
  I2C_DMA_REQUEST_TX = 0x00,
  I2C_DMA_REQUEST_RX = 0x01
} i2c_dma_request_type;




typedef enum
{
  I2C_SMBUS_ALERT_HIGH = 0x00,
  I2C_SMBUS_ALERT_LOW = 0x01
} i2c_smbus_alert_set_type;




typedef enum
{
  I2C_TIMEOUT_DETCET_LOW = 0x00,
  I2C_TIMEOUT_DETCET_HIGH = 0x01
} i2c_timeout_detcet_type;




typedef enum
{
  I2C_ADDR2_NOMASK = 0x00,
  I2C_ADDR2_MASK01 = 0x01,
  I2C_ADDR2_MASK02 = 0x02,
  I2C_ADDR2_MASK03 = 0x03,
  I2C_ADDR2_MASK04 = 0x04,
  I2C_ADDR2_MASK05 = 0x05,
  I2C_ADDR2_MASK06 = 0x06,
  I2C_ADDR2_MASK07 = 0x07
} i2c_addr2_mask_type;




typedef enum
{
  I2C_AUTO_STOP_MODE = 0x02000000,
  I2C_SOFT_STOP_MODE = 0x00000000,
  I2C_RELOAD_MODE = 0x01000000
} i2c_reload_stop_mode_type;




typedef enum
{
  I2C_WITHOUT_START = 0x00000000,
  I2C_GEN_START_READ = 0x00002400,
  I2C_GEN_START_WRITE = 0x00002000
} i2c_start_mode_type;




typedef struct
{



  union
  {
    volatile uint32_t ctrl1;
    struct
    {
      volatile uint32_t i2cen : 1;
      volatile uint32_t tdien : 1;
      volatile uint32_t rdien : 1;
      volatile uint32_t addrien : 1;
      volatile uint32_t ackfailien : 1;
      volatile uint32_t stopien : 1;
      volatile uint32_t tdcien : 1;
      volatile uint32_t errien : 1;
      volatile uint32_t dflt : 4;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t dmaten : 1;
      volatile uint32_t dmaren : 1;
      volatile uint32_t sctrl : 1;
      volatile uint32_t stretch : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t gcaen : 1;
      volatile uint32_t haddren : 1;
      volatile uint32_t devaddren : 1;
      volatile uint32_t smbalert : 1;
      volatile uint32_t pecen : 1;
      volatile uint32_t reserved3 : 8;
    } ctrl1_bit;
  };




  union
  {
    volatile uint32_t ctrl2;
    struct
    {
      volatile uint32_t saddr : 10;
      volatile uint32_t dir : 1;
      volatile uint32_t addr10 : 1;
      volatile uint32_t readh10 : 1;
      volatile uint32_t genstart : 1;
      volatile uint32_t genstop : 1;
      volatile uint32_t nacken : 1;
      volatile uint32_t cnt : 8;
      volatile uint32_t rlden : 1;
      volatile uint32_t astopen : 1;
      volatile uint32_t pecten : 1;
      volatile uint32_t reserved1 : 5;
    } ctrl2_bit;
  };




  union
  {
    volatile uint32_t oaddr1;
    struct
    {
      volatile uint32_t addr1 : 10;
      volatile uint32_t addr1mode : 1;
      volatile uint32_t reserved1 : 4;
      volatile uint32_t addr1en : 1;
      volatile uint32_t reserved2 : 16;
    } oaddr1_bit;
  };




  union
  {
    volatile uint32_t oaddr2;
    struct
    {
      volatile uint32_t reserved1 : 1;
      volatile uint32_t addr2 : 7;
      volatile uint32_t addr2mask : 3;
      volatile uint32_t reserved2 : 4;
      volatile uint32_t addr2en : 1;
      volatile uint32_t reserved3 : 16;
    } oaddr2_bit;
  };




  union
  {
    volatile uint32_t clkctrl;
    struct
    {
      volatile uint32_t scll : 8;
      volatile uint32_t sclh : 8;
      volatile uint32_t sdad : 4;
      volatile uint32_t scld : 4;
      volatile uint32_t divh : 4;
      volatile uint32_t divl : 4;
    } clkctrl_bit;
  };




  union
  {
    volatile uint32_t timeout;
    struct
    {
      volatile uint32_t totime : 12;
      volatile uint32_t tomode : 1;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t toen : 1;
      volatile uint32_t exttime : 12;
      volatile uint32_t reserved2 : 3;
      volatile uint32_t exten : 1;
    } timeout_bit;
  };




  union
  {
    volatile uint32_t sts;
    struct
    {
      volatile uint32_t tdbe : 1;
      volatile uint32_t tdis : 1;
      volatile uint32_t rdbf : 1;
      volatile uint32_t addrf : 1;
      volatile uint32_t ackfail : 1;
      volatile uint32_t stopf : 1;
      volatile uint32_t tdc : 1;
      volatile uint32_t tcrld : 1;
      volatile uint32_t buserr : 1;
      volatile uint32_t arlost : 1;
      volatile uint32_t ouf : 1;
      volatile uint32_t pecerr : 1;
      volatile uint32_t tmout : 1;
      volatile uint32_t alertf : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t busyf : 1;
      volatile uint32_t sdir : 1;
      volatile uint32_t addr : 7;
      volatile uint32_t reserved2 : 8;
    } sts_bit;
  };




  union
  {
    volatile uint32_t clr;
    struct
    {
      volatile uint32_t reserved1 : 3;
      volatile uint32_t addrc : 1;
      volatile uint32_t ackfailc : 1;
      volatile uint32_t stopc : 1;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t buserrc : 1;
      volatile uint32_t arlostc : 1;
      volatile uint32_t oufc : 1;
      volatile uint32_t pecerrc : 1;
      volatile uint32_t tmoutc : 1;
      volatile uint32_t alertc : 1;
      volatile uint32_t reserved3 : 18;
    } clr_bit;
  };




  union
  {
    volatile uint32_t pec;
    struct
    {
      volatile uint32_t pecval : 8;
      volatile uint32_t reserved1 : 24;
    } pec_bit;
  };




  union
  {
    volatile uint32_t rxdt;
    struct
    {
      volatile uint32_t dt : 8;
      volatile uint32_t reserved1 : 24;
    } rxdt_bit;
  };




  union
  {
    volatile uint32_t txdt;
    struct
    {
      volatile uint32_t dt : 8;
      volatile uint32_t reserved1 : 24;
    } txdt_bit;
  };

} i2c_type;
# 422 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_i2c.h"
void i2c_reset(i2c_type *i2c_x);
void i2c_init(i2c_type *i2c_x, uint8_t dfilters, uint32_t clk);
void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address);
void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask);
void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_smbus_enable(i2c_type *i2c_x, i2c_smbus_mode_type mode, confirm_state new_state);
void i2c_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_addr10_mode_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_transfer_addr_set(i2c_type *i2c_x, uint16_t address);
uint16_t i2c_transfer_addr_get(i2c_type *i2c_x);
void i2c_transfer_dir_set(i2c_type *i2c_x, i2c_transfer_dir_type i2c_direction);
i2c_transfer_dir_type i2c_transfer_dir_get(i2c_type *i2c_x);
uint8_t i2c_matched_addr_get(i2c_type *i2c_x);
void i2c_auto_stop_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_reload_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_cnt_set(i2c_type *i2c_x, uint8_t cnt);
void i2c_addr10_header_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level);
void i2c_slave_data_ctrl_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state);
uint8_t i2c_pec_value_get(i2c_type *i2c_x);
void i2c_timeout_set(i2c_type *i2c_x, uint16_t timeout);
void i2c_timeout_detcet_set(i2c_type *i2c_x, i2c_timeout_detcet_type mode);
void i2c_timeout_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_ext_timeout_set(i2c_type *i2c_x, uint16_t timeout);
void i2c_ext_timeout_enable(i2c_type *i2c_x, confirm_state new_state);
void i2c_interrupt_enable(i2c_type *i2c_x, uint32_t source, confirm_state new_state);
flag_status i2c_interrupt_get(i2c_type *i2c_x, uint16_t source);
void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state new_state);
void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_mode_type start);
void i2c_start_generate(i2c_type *i2c_x);
void i2c_stop_generate(i2c_type *i2c_x);
void i2c_data_send(i2c_type *i2c_x, uint8_t data);
uint8_t i2c_data_receive(i2c_type *i2c_x);
flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag);
void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag);
# 97 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_usart.h" 1
# 92 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_usart.h"
typedef enum
{
  USART_PARITY_NONE = 0x00,
  USART_PARITY_EVEN = 0x01,
  USART_PARITY_ODD = 0x02
} usart_parity_selection_type;




typedef enum
{
  USART_WAKEUP_BY_IDLE_FRAME = 0x00,
  USART_WAKEUP_BY_MATCHING_ID = 0x01
} usart_wakeup_mode_type;




typedef enum
{
  USART_DATA_7BITS = 0x00,
  USART_DATA_8BITS = 0x01,
  USART_DATA_9BITS = 0x02
} usart_data_bit_num_type;




typedef enum
{
  USART_BREAK_10BITS = 0x00,
  USART_BREAK_11BITS = 0x01
} usart_break_bit_num_type;




typedef enum
{
  USART_CLOCK_PHASE_1EDGE = 0x00,
  USART_CLOCK_PHASE_2EDGE = 0x01
} usart_clock_phase_type;




typedef enum
{
  USART_CLOCK_POLARITY_LOW = 0x00,
  USART_CLOCK_POLARITY_HIGH = 0x01
} usart_clock_polarity_type;




typedef enum
{
  USART_CLOCK_LAST_BIT_NONE = 0x00,
  USART_CLOCK_LAST_BIT_OUTPUT = 0x01
} usart_lbcp_type;




typedef enum
{
  USART_STOP_1_BIT = 0x00,
  USART_STOP_0_5_BIT = 0x01,
  USART_STOP_2_BIT = 0x02,
  USART_STOP_1_5_BIT = 0x03
} usart_stop_bit_num_type;




typedef enum
{
  USART_HARDWARE_FLOW_NONE = 0x00,
  USART_HARDWARE_FLOW_RTS = 0x01,
  USART_HARDWARE_FLOW_CTS = 0x02,
  USART_HARDWARE_FLOW_RTS_CTS = 0x03
} usart_hardware_flow_control_type;




typedef enum
{
  USART_ID_FIXED_4_BIT = 0x00,
  USART_ID_RELATED_DATA_BIT = 0x01
} usart_identification_bit_num_type;




typedef enum
{
  USART_DE_POLARITY_HIGH = 0x00,
  USART_DE_POLARITY_LOW = 0x01
} usart_de_polarity_type;




typedef struct
{



  union
  {
    volatile uint32_t sts;
    struct
    {
      volatile uint32_t perr : 1;
      volatile uint32_t ferr : 1;
      volatile uint32_t nerr : 1;
      volatile uint32_t roerr : 1;
      volatile uint32_t idlef : 1;
      volatile uint32_t rdbf : 1;
      volatile uint32_t tdc : 1;
      volatile uint32_t tdbe : 1;
      volatile uint32_t bff : 1;
      volatile uint32_t ctscf : 1;
      volatile uint32_t reserved1 : 22;
    } sts_bit;
  };




  union
  {
    volatile uint32_t dt;
    struct
    {
      volatile uint32_t dt : 9;
      volatile uint32_t reserved1 : 23;
    } dt_bit;
  };




  union
  {
    volatile uint32_t baudr;
    struct
    {
      volatile uint32_t div : 16;
      volatile uint32_t reserved1 : 16;
    } baudr_bit;
  };




  union
  {
    volatile uint32_t ctrl1;
    struct
    {
      volatile uint32_t sbf : 1;
      volatile uint32_t rm : 1;
      volatile uint32_t ren : 1;
      volatile uint32_t ten : 1;
      volatile uint32_t idleien : 1;
      volatile uint32_t rdbfien : 1;
      volatile uint32_t tdcien : 1;
      volatile uint32_t tdbeien : 1;
      volatile uint32_t perrien : 1;
      volatile uint32_t psel : 1;
      volatile uint32_t pen : 1;
      volatile uint32_t wum : 1;
      volatile uint32_t dbn_l : 1;
      volatile uint32_t uen : 1;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t tcdt : 5;
      volatile uint32_t tsdt : 5;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t dbn_h : 1;
      volatile uint32_t reserved3 : 3;
    } ctrl1_bit;
  };




  union
  {
    volatile uint32_t ctrl2;
    struct
    {
      volatile uint32_t id_l : 4;
      volatile uint32_t idbn : 1;
      volatile uint32_t bfbn : 1;
      volatile uint32_t bfien : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t lbcp : 1;
      volatile uint32_t clkpha : 1;
      volatile uint32_t clkpol : 1;
      volatile uint32_t clken : 1;
      volatile uint32_t stopbn : 2;
      volatile uint32_t linen : 1;
      volatile uint32_t trpswap : 1;
      volatile uint32_t reserved2 : 12;
      volatile uint32_t id_h : 4;
    } ctrl2_bit;
  };




  union
  {
    volatile uint32_t ctrl3;
    struct
    {
      volatile uint32_t errien : 1;
      volatile uint32_t irdaen : 1;
      volatile uint32_t irdalp : 1;
      volatile uint32_t slben : 1;
      volatile uint32_t scnacken : 1;
      volatile uint32_t scmen : 1;
      volatile uint32_t dmaren : 1;
      volatile uint32_t dmaten : 1;
      volatile uint32_t rtsen : 1;
      volatile uint32_t ctsen : 1;
      volatile uint32_t ctscfien : 1;
      volatile uint32_t reserved1 : 3;
      volatile uint32_t rs485en : 1;
      volatile uint32_t dep : 1;
      volatile uint32_t reserved2 : 16;
    } ctrl3_bit;
  };




  union
  {
    volatile uint32_t gdiv;
    struct
    {
      volatile uint32_t isdiv : 8;
      volatile uint32_t scgt : 8;
      volatile uint32_t reserved1 : 16;
    } gdiv_bit;
  };
} usart_type;
# 361 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_usart.h"
void usart_reset(usart_type* usart_x);
void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit);
void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity);
void usart_enable(usart_type* usart_x, confirm_state new_state);
void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state);
void usart_receiver_enable(usart_type* usart_x, confirm_state new_state);
void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb);
void usart_clock_enable(usart_type* usart_x, confirm_state new_state);
void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state);
void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state);
void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state);
void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id);
void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode);
void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state);
void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit);
void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state);
void usart_data_transmit(usart_type* usart_x, uint16_t data);
uint16_t usart_data_receive(usart_type* usart_x);
void usart_break_send(usart_type* usart_x);
void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val);
void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val);
void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state);
void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state);
void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state);
void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state);
void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state);
void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state);
flag_status usart_flag_get(usart_type* usart_x, uint32_t flag);
void usart_flag_clear(usart_type* usart_x, uint32_t flag);
void usart_rs485_delay_time_config(usart_type* usart_x, uint8_t start_delay_time, uint8_t complete_delay_time);
void usart_transmit_receive_pin_swap(usart_type* usart_x, confirm_state new_state);
void usart_id_bit_num_set(usart_type* usart_x, usart_identification_bit_num_type id_bit_num);
void usart_de_polarity_set(usart_type* usart_x, usart_de_polarity_type de_polarity);
void usart_rs485_mode_enable(usart_type* usart_x, confirm_state new_state);
# 100 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_pwc.h" 1
# 86 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_pwc.h"
typedef enum
{
  PWC_PVM_VOLTAGE_2V3 = 0x01,
  PWC_PVM_VOLTAGE_2V4 = 0x02,
  PWC_PVM_VOLTAGE_2V5 = 0x03,
  PWC_PVM_VOLTAGE_2V6 = 0x04,
  PWC_PVM_VOLTAGE_2V7 = 0x05,
  PWC_PVM_VOLTAGE_2V8 = 0x06,
  PWC_PVM_VOLTAGE_2V9 = 0x07
} pwc_pvm_voltage_type;




typedef enum
{
  PWC_LDO_OUTPUT_1V3 = 0x01,
  PWC_LDO_OUTPUT_1V2 = 0x00,
  PWC_LDO_OUTPUT_1V1 = 0x04,
  PWC_LDO_OUTPUT_1V0 = 0x05,
} pwc_ldo_output_voltage_type;




typedef enum
{
  PWC_SLEEP_ENTER_WFI = 0x00,
  PWC_SLEEP_ENTER_WFE = 0x01
} pwc_sleep_enter_type ;




typedef enum
{
  PWC_DEEP_SLEEP_ENTER_WFI = 0x00,
  PWC_DEEP_SLEEP_ENTER_WFE = 0x01
} pwc_deep_sleep_enter_type ;




typedef enum
{
  PWC_REGULATOR_ON = 0x00,
  PWC_REGULATOR_LOW_POWER = 0x01
} pwc_regulator_type ;




typedef struct
{



  union
  {
    volatile uint32_t ctrl;
    struct
    {
      volatile uint32_t vrsel : 1;
      volatile uint32_t lpsel : 1;
      volatile uint32_t clswef : 1;
      volatile uint32_t clsef : 1;
      volatile uint32_t pvmen : 1;
      volatile uint32_t pvmsel : 3;
      volatile uint32_t bpwen : 1;
      volatile uint32_t reserved1 : 23;
    } ctrl_bit;
  };




  union
  {
    volatile uint32_t ctrlsts;
    struct
    {
      volatile uint32_t swef : 1;
      volatile uint32_t sef : 1;
      volatile uint32_t pvmof : 1;
      volatile uint32_t reserved1 : 5;
      volatile uint32_t swpen1 : 1;
      volatile uint32_t swpen2 : 1;
      volatile uint32_t reserved2 : 22;
    } ctrlsts_bit;
  };

  volatile uint32_t reserved1[2];




  union
  {
    volatile uint32_t ldoov;
    struct
    {
      volatile uint32_t ldoovsel : 3;
      volatile uint32_t reserved1 : 29;
    } ldoov_bit;
  };

} pwc_type;
# 204 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_pwc.h"
void pwc_reset(void);
void pwc_battery_powered_domain_access(confirm_state new_state);
void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage);
void pwc_power_voltage_monitor_enable(confirm_state new_state);
void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state);
void pwc_flag_clear(uint32_t pwc_flag);
flag_status pwc_flag_get(uint32_t pwc_flag);
void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter);
void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter);
void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator);
void pwc_standby_mode_enter(void);
# 103 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_can.h" 1
# 136 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_can.h"
typedef enum
{
  CAN_FILTER_FIFO0 = 0x00,
  CAN_FILTER_FIFO1 = 0x01
} can_filter_fifo_type;




typedef enum
{
  CAN_FILTER_MODE_ID_MASK = 0x00,
  CAN_FILTER_MODE_ID_LIST = 0x01
} can_filter_mode_type;




typedef enum
{
  CAN_FILTER_16BIT = 0x00,
  CAN_FILTER_32BIT = 0x01
} can_filter_bit_width_type;




typedef enum
{
  CAN_MODE_COMMUNICATE = 0x00,
  CAN_MODE_LOOPBACK = 0x01,
  CAN_MODE_LISTENONLY = 0x02,
  CAN_MODE_LISTENONLY_LOOPBACK = 0x03
} can_mode_type;




typedef enum
{
  CAN_OPERATINGMODE_FREEZE = 0x00,
  CAN_OPERATINGMODE_DOZE = 0x01,
  CAN_OPERATINGMODE_COMMUNICATE = 0x02
} can_operating_mode_type;




typedef enum
{
  CAN_RSAW_1TQ = 0x00,
  CAN_RSAW_2TQ = 0x01,
  CAN_RSAW_3TQ = 0x02,
  CAN_RSAW_4TQ = 0x03
} can_rsaw_type;




typedef enum
{
  CAN_BTS1_1TQ = 0x00,
  CAN_BTS1_2TQ = 0x01,
  CAN_BTS1_3TQ = 0x02,
  CAN_BTS1_4TQ = 0x03,
  CAN_BTS1_5TQ = 0x04,
  CAN_BTS1_6TQ = 0x05,
  CAN_BTS1_7TQ = 0x06,
  CAN_BTS1_8TQ = 0x07,
  CAN_BTS1_9TQ = 0x08,
  CAN_BTS1_10TQ = 0x09,
  CAN_BTS1_11TQ = 0x0A,
  CAN_BTS1_12TQ = 0x0B,
  CAN_BTS1_13TQ = 0x0C,
  CAN_BTS1_14TQ = 0x0D,
  CAN_BTS1_15TQ = 0x0E,
  CAN_BTS1_16TQ = 0x0F
} can_bts1_type;




typedef enum
{
  CAN_BTS2_1TQ = 0x00,
  CAN_BTS2_2TQ = 0x01,
  CAN_BTS2_3TQ = 0x02,
  CAN_BTS2_4TQ = 0x03,
  CAN_BTS2_5TQ = 0x04,
  CAN_BTS2_6TQ = 0x05,
  CAN_BTS2_7TQ = 0x06,
  CAN_BTS2_8TQ = 0x07
} can_bts2_type;




typedef enum
{
  CAN_ID_STANDARD = 0x00,
  CAN_ID_EXTENDED = 0x01
} can_identifier_type;




typedef enum
{
  CAN_TFT_DATA = 0x00,
  CAN_TFT_REMOTE = 0x01
} can_trans_frame_type;




typedef enum
{
  CAN_TX_MAILBOX0 = 0x00,
  CAN_TX_MAILBOX1 = 0x01,
  CAN_TX_MAILBOX2 = 0x02
} can_tx_mailbox_num_type;




typedef enum
{
  CAN_RX_FIFO0 = 0x00,
  CAN_RX_FIFO1 = 0x01
} can_rx_fifo_num_type;




typedef enum
{
  CAN_TX_STATUS_FAILED = 0x00,
  CAN_TX_STATUS_SUCCESSFUL = 0x01,
  CAN_TX_STATUS_PENDING = 0x02,
  CAN_TX_STATUS_NO_EMPTY = 0x04
} can_transmit_status_type;




typedef enum
{
  CAN_ENTER_DOZE_FAILED = 0x00,
  CAN_ENTER_DOZE_SUCCESSFUL = 0x01
} can_enter_doze_status_type;




typedef enum
{
  CAN_QUIT_DOZE_FAILED = 0x00,
  CAN_QUIT_DOZE_SUCCESSFUL = 0x01
} can_quit_doze_status_type;




typedef enum
{
  CAN_DISCARDING_FIRST_RECEIVED = 0x00,
  CAN_DISCARDING_LAST_RECEIVED = 0x01
} can_msg_discarding_rule_type;




typedef enum
{
  CAN_SENDING_BY_ID = 0x00,
  CAN_SENDING_BY_REQUEST = 0x01
} can_msg_sending_rule_type;




typedef enum
{
  CAN_ERRORRECORD_NOERR = 0x00,
  CAN_ERRORRECORD_STUFFERR = 0x01,
  CAN_ERRORRECORD_FORMERR = 0x02,
  CAN_ERRORRECORD_ACKERR = 0x03,
  CAN_ERRORRECORD_BITRECESSIVEERR = 0x04,
  CAN_ERRORRECORD_BITDOMINANTERR = 0x05,
  CAN_ERRORRECORD_CRCERR = 0x06,
  CAN_ERRORRECORD_SOFTWARESETERR = 0x07
} can_error_record_type;




typedef struct
{
  can_mode_type mode_selection;

  confirm_state ttc_enable;

  confirm_state aebo_enable;

  confirm_state aed_enable;

  confirm_state prsf_enable;

  can_msg_discarding_rule_type mdrsel_selection;

  can_msg_sending_rule_type mmssr_selection;

} can_base_type;




typedef struct
{
  uint16_t baudrate_div;

  can_rsaw_type rsaw_size;

  can_bts1_type bts1_size;

  can_bts2_type bts2_size;

} can_baudrate_type;




typedef struct
{
  confirm_state filter_activate_enable;

  can_filter_mode_type filter_mode;

  can_filter_fifo_type filter_fifo;

  uint8_t filter_number;

  can_filter_bit_width_type filter_bit;

  uint16_t filter_id_high;


  uint16_t filter_id_low;


  uint16_t filter_mask_high;


  uint16_t filter_mask_low;

} can_filter_init_type;




typedef struct
{
  uint32_t standard_id;


  uint32_t extended_id;


  can_identifier_type id_type;

  can_trans_frame_type frame_type;

  uint8_t dlc;


  uint8_t data[8];

} can_tx_message_type;




typedef struct
{
    uint32_t standard_id;


    uint32_t extended_id;


    can_identifier_type id_type;

    can_trans_frame_type frame_type;

    uint8_t dlc;


    uint8_t data[8];

    uint8_t filter_index;

} can_rx_message_type;




typedef struct
{



  union
  {
    volatile uint32_t tmi;
    struct
    {
      volatile uint32_t tmsr : 1;
      volatile uint32_t tmfrsel : 1;
      volatile uint32_t tmidsel : 1;
      volatile uint32_t tmeid : 18;
      volatile uint32_t tmsid : 11;
    } tmi_bit;
  };




  union
  {
    volatile uint32_t tmc;
    struct
    {
      volatile uint32_t tmdtbl : 4;
      volatile uint32_t reserved1 : 4;
      volatile uint32_t tmtsten : 1;
      volatile uint32_t reserved2 : 7;
      volatile uint32_t tmts : 16;
    } tmc_bit;
  };




  union
  {
    volatile uint32_t tmdtl;
    struct
    {
      volatile uint32_t tmdt0 : 8;
      volatile uint32_t tmdt1 : 8;
      volatile uint32_t tmdt2 : 8;
      volatile uint32_t tmdt3 : 8;
    } tmdtl_bit;
  };




  union
  {
    volatile uint32_t tmdth;
    struct
    {
      volatile uint32_t tmdt4 : 8;
      volatile uint32_t tmdt5 : 8;
      volatile uint32_t tmdt6 : 8;
      volatile uint32_t tmdt7 : 8;
    } tmdth_bit;
  };
} can_tx_mailbox_type;




typedef struct
{



  union
  {
    volatile uint32_t rfi;
    struct
    {
      volatile uint32_t reserved1 : 1;
      volatile uint32_t rffri : 1;
      volatile uint32_t rfidi : 1;
      volatile uint32_t rfeid : 18;
      volatile uint32_t rfsid : 11;
    } rfi_bit;
  };




  union
  {
    volatile uint32_t rfc;
    struct
    {
      volatile uint32_t rfdtl : 4;
      volatile uint32_t reserved1 : 4;
      volatile uint32_t rffmn : 8;
      volatile uint32_t rfts : 16;
    } rfc_bit;
  };




  union
  {
    volatile uint32_t rfdtl;
    struct
    {
      volatile uint32_t rfdt0 : 8;
      volatile uint32_t rfdt1 : 8;
      volatile uint32_t rfdt2 : 8;
      volatile uint32_t rfdt3 : 8;
    } rfdtl_bit;
  };




  union
  {
    volatile uint32_t rfdth;
    struct
    {
      volatile uint32_t rfdt4 : 8;
      volatile uint32_t rfdt5 : 8;
      volatile uint32_t rfdt6 : 8;
      volatile uint32_t rfdt7 : 8;
    } rfdth_bit;
  };
} can_fifo_mailbox_type;




typedef struct
{
  volatile uint32_t ffdb1;
  volatile uint32_t ffdb2;
} can_filter_register_type;




typedef struct
{




  union
  {
    volatile uint32_t mctrl;
    struct
    {
      volatile uint32_t fzen : 1;
      volatile uint32_t dzen : 1;
      volatile uint32_t mmssr : 1;
      volatile uint32_t mdrsel : 1;
      volatile uint32_t prsfen : 1;
      volatile uint32_t aeden : 1;
      volatile uint32_t aeboen : 1;
      volatile uint32_t ttcen : 1;
      volatile uint32_t reserved1 : 7;
      volatile uint32_t sprst : 1;
      volatile uint32_t ptd : 1;
      volatile uint32_t reserved2 : 15;
    } mctrl_bit;
  };




  union
  {
    volatile uint32_t msts;
    struct
    {
      volatile uint32_t fzc : 1;
      volatile uint32_t dzc : 1;
      volatile uint32_t eoif : 1;
      volatile uint32_t qdzif : 1;
      volatile uint32_t edzif : 1;
      volatile uint32_t reserved1 : 3;
      volatile uint32_t cuss : 1;
      volatile uint32_t curs : 1;
      volatile uint32_t lsamprx : 1;
      volatile uint32_t realrx : 1;
      volatile uint32_t reserved2 : 20;
    } msts_bit;
  };




  union
  {
    volatile uint32_t tsts;
    struct
    {
      volatile uint32_t tm0tcf : 1;
      volatile uint32_t tm0tsf : 1;
      volatile uint32_t tm0alf : 1;
      volatile uint32_t tm0tef : 1;
      volatile uint32_t reserved1 : 3;
      volatile uint32_t tm0ct : 1;
      volatile uint32_t tm1tcf : 1;
      volatile uint32_t tm1tsf : 1;
      volatile uint32_t tm1alf : 1;
      volatile uint32_t tm1tef : 1;
      volatile uint32_t reserved2 : 3;
      volatile uint32_t tm1ct : 1;
      volatile uint32_t tm2tcf : 1;
      volatile uint32_t tm2tsf : 1;
      volatile uint32_t tm2alf : 1;
      volatile uint32_t tm2tef : 1;
      volatile uint32_t reserved3 : 3;
      volatile uint32_t tm2ct : 1;
      volatile uint32_t tmnr : 2;
      volatile uint32_t tm0ef : 1;
      volatile uint32_t tm1ef : 1;
      volatile uint32_t tm2ef : 1;
      volatile uint32_t tm0lpf : 1;
      volatile uint32_t tm1lpf : 1;
      volatile uint32_t tm2lpf : 1;
    } tsts_bit;
  };




  union
  {
    volatile uint32_t rf0;
    struct
    {
      volatile uint32_t rf0mn : 2;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t rf0ff : 1;
      volatile uint32_t rf0of : 1;
      volatile uint32_t rf0r : 1;
      volatile uint32_t reserved2 : 26;
    } rf0_bit;
  };




  union
  {
    volatile uint32_t rf1;
    struct
    {
      volatile uint32_t rf1mn : 2;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t rf1ff : 1;
      volatile uint32_t rf1of : 1;
      volatile uint32_t rf1r : 1;
      volatile uint32_t reserved2 : 26;
    } rf1_bit;
  };




  union
  {
    volatile uint32_t inten;
    struct
    {
      volatile uint32_t tcien : 1;
      volatile uint32_t rf0mien : 1;
      volatile uint32_t rf0fien : 1;
      volatile uint32_t rf0oien : 1;
      volatile uint32_t rf1mien : 1;
      volatile uint32_t rf1fien : 1;
      volatile uint32_t rf1oien : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t eaien : 1;
      volatile uint32_t epien : 1;
      volatile uint32_t boien : 1;
      volatile uint32_t etrien : 1;
      volatile uint32_t reserved2 : 3;
      volatile uint32_t eoien : 1;
      volatile uint32_t qdzien : 1;
      volatile uint32_t edzien : 1;
      volatile uint32_t reserved3 : 14;
    } inten_bit;
  };




  union
  {
    volatile uint32_t ests;
    struct
    {
      volatile uint32_t eaf : 1;
      volatile uint32_t epf : 1;
      volatile uint32_t bof : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t etr : 3;
      volatile uint32_t reserved2 : 9;
      volatile uint32_t tec : 8;
      volatile uint32_t rec : 8;
    } ests_bit;
  };




  union
  {
    volatile uint32_t btmg;
    struct
    {
      volatile uint32_t brdiv : 12;
      volatile uint32_t reserved1 : 4;
      volatile uint32_t bts1 : 4;
      volatile uint32_t bts2 : 3;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t rsaw : 2;
      volatile uint32_t reserved3 : 4;
      volatile uint32_t lben : 1;
      volatile uint32_t loen : 1;
    } btmg_bit;
  };




  volatile uint32_t reserved1[88];




  can_tx_mailbox_type tx_mailbox[3];




  can_fifo_mailbox_type fifo_mailbox[2];




  volatile uint32_t reserved2[12];




  union
  {
    volatile uint32_t fctrl;
    struct
    {
      volatile uint32_t fcs : 1;
      volatile uint32_t reserved1 : 31;
    } fctrl_bit;
  };




  union
  {
    volatile uint32_t fmcfg;
    struct
    {
      volatile uint32_t fmsel0 : 1;
      volatile uint32_t fmsel1 : 1;
      volatile uint32_t fmsel2 : 1;
      volatile uint32_t fmsel3 : 1;
      volatile uint32_t fmsel4 : 1;
      volatile uint32_t fmsel5 : 1;
      volatile uint32_t fmsel6 : 1;
      volatile uint32_t fmsel7 : 1;
      volatile uint32_t fmsel8 : 1;
      volatile uint32_t fmsel9 : 1;
      volatile uint32_t fmsel10 : 1;
      volatile uint32_t fmsel11 : 1;
      volatile uint32_t fmsel12 : 1;
      volatile uint32_t fmsel13 : 1;
      volatile uint32_t fmsel14 : 1;
      volatile uint32_t fmsel15 : 1;
      volatile uint32_t fmsel16 : 1;
      volatile uint32_t fmsel17 : 1;
      volatile uint32_t fmsel18 : 1;
      volatile uint32_t fmsel19 : 1;
      volatile uint32_t fmsel20 : 1;
      volatile uint32_t fmsel21 : 1;
      volatile uint32_t fmsel22 : 1;
      volatile uint32_t fmsel23 : 1;
      volatile uint32_t fmsel24 : 1;
      volatile uint32_t fmsel25 : 1;
      volatile uint32_t fmsel26 : 1;
      volatile uint32_t fmsel27 : 1;
      volatile uint32_t reserved1 : 4;
    } fmcfg_bit;
  };




  volatile uint32_t reserved3;




  union
  {
    volatile uint32_t fbwcfg;
    struct
    {
      volatile uint32_t fbwsel0 : 1;
      volatile uint32_t fbwsel1 : 1;
      volatile uint32_t fbwsel2 : 1;
      volatile uint32_t fbwsel3 : 1;
      volatile uint32_t fbwsel4 : 1;
      volatile uint32_t fbwsel5 : 1;
      volatile uint32_t fbwsel6 : 1;
      volatile uint32_t fbwsel7 : 1;
      volatile uint32_t fbwsel8 : 1;
      volatile uint32_t fbwsel9 : 1;
      volatile uint32_t fbwsel10 : 1;
      volatile uint32_t fbwsel11 : 1;
      volatile uint32_t fbwsel12 : 1;
      volatile uint32_t fbwsel13 : 1;
      volatile uint32_t fbwsel14 : 1;
      volatile uint32_t fbwsel15 : 1;
      volatile uint32_t fbwsel16 : 1;
      volatile uint32_t fbwsel17 : 1;
      volatile uint32_t fbwsel18 : 1;
      volatile uint32_t fbwsel19 : 1;
      volatile uint32_t fbwsel20 : 1;
      volatile uint32_t fbwsel21 : 1;
      volatile uint32_t fbwsel22 : 1;
      volatile uint32_t fbwsel23 : 1;
      volatile uint32_t fbwsel24 : 1;
      volatile uint32_t fbwsel25 : 1;
      volatile uint32_t fbwsel26 : 1;
      volatile uint32_t fbwsel27 : 1;
      volatile uint32_t reserved1 : 4;
    } fbwcfg_bit;
  };




  volatile uint32_t reserved4;




  union
  {
    volatile uint32_t frf;
    struct
    {
      volatile uint32_t frfsel0 : 1;
      volatile uint32_t frfsel1 : 1;
      volatile uint32_t frfsel2 : 1;
      volatile uint32_t frfsel3 : 1;
      volatile uint32_t frfsel4 : 1;
      volatile uint32_t frfsel5 : 1;
      volatile uint32_t frfsel6 : 1;
      volatile uint32_t frfsel7 : 1;
      volatile uint32_t frfsel8 : 1;
      volatile uint32_t frfsel9 : 1;
      volatile uint32_t frfsel10 : 1;
      volatile uint32_t frfsel11 : 1;
      volatile uint32_t frfsel12 : 1;
      volatile uint32_t frfsel13 : 1;
      volatile uint32_t frfsel14 : 1;
      volatile uint32_t frfsel15 : 1;
      volatile uint32_t frfsel16 : 1;
      volatile uint32_t frfsel17 : 1;
      volatile uint32_t frfsel18 : 1;
      volatile uint32_t frfsel19 : 1;
      volatile uint32_t frfsel20 : 1;
      volatile uint32_t frfsel21 : 1;
      volatile uint32_t frfsel22 : 1;
      volatile uint32_t frfsel23 : 1;
      volatile uint32_t frfsel24 : 1;
      volatile uint32_t frfsel25 : 1;
      volatile uint32_t frfsel26 : 1;
      volatile uint32_t frfsel27 : 1;
      volatile uint32_t reserved1 : 4;
    } frf_bit;
  };




  volatile uint32_t reserved5;




  union
  {
    volatile uint32_t facfg;
    struct
    {
      volatile uint32_t faen0 : 1;
      volatile uint32_t faen1 : 1;
      volatile uint32_t faen2 : 1;
      volatile uint32_t faen3 : 1;
      volatile uint32_t faen4 : 1;
      volatile uint32_t faen5 : 1;
      volatile uint32_t faen6 : 1;
      volatile uint32_t faen7 : 1;
      volatile uint32_t faen8 : 1;
      volatile uint32_t faen9 : 1;
      volatile uint32_t faen10 : 1;
      volatile uint32_t faen11 : 1;
      volatile uint32_t faen12 : 1;
      volatile uint32_t faen13 : 1;
      volatile uint32_t faen14 : 1;
      volatile uint32_t faen15 : 1;
      volatile uint32_t faen16 : 1;
      volatile uint32_t faen17 : 1;
      volatile uint32_t faen18 : 1;
      volatile uint32_t faen19 : 1;
      volatile uint32_t faen20 : 1;
      volatile uint32_t faen21 : 1;
      volatile uint32_t faen22 : 1;
      volatile uint32_t faen23 : 1;
      volatile uint32_t faen24 : 1;
      volatile uint32_t faen25 : 1;
      volatile uint32_t faen26 : 1;
      volatile uint32_t faen27 : 1;
      volatile uint32_t reserved1 : 4;
    } facfg_bit;
  };




  volatile uint32_t reserved6[8];




  can_filter_register_type ffb[28];
} can_type;
# 1001 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_can.h"
void can_reset(can_type* can_x);
void can_baudrate_default_para_init(can_baudrate_type* can_baudrate_struct);
error_status can_baudrate_set(can_type* can_x, can_baudrate_type* can_baudrate_struct);
void can_default_para_init(can_base_type* can_base_struct);
error_status can_base_init(can_type* can_x, can_base_type* can_base_struct);
void can_filter_default_para_init(can_filter_init_type* can_filter_init_struct);
void can_filter_init(can_type* can_x, can_filter_init_type* can_filter_init_struct);
void can_debug_transmission_prohibit(can_type* can_x, confirm_state new_state);
void can_ttc_mode_enable(can_type* can_x, confirm_state new_state);
uint8_t can_message_transmit(can_type* can_x, can_tx_message_type* tx_message_struct);
can_transmit_status_type can_transmit_status_get(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox);
void can_transmit_cancel(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox);
void can_message_receive(can_type* can_x, can_rx_fifo_num_type fifo_number, can_rx_message_type* rx_message_struct);
void can_receive_fifo_release(can_type* can_x, can_rx_fifo_num_type fifo_number);
uint8_t can_receive_message_pending_get(can_type* can_x, can_rx_fifo_num_type fifo_number);
error_status can_operating_mode_set(can_type* can_x, can_operating_mode_type can_operating_mode);
can_enter_doze_status_type can_doze_mode_enter(can_type* can_x);
can_quit_doze_status_type can_doze_mode_exit(can_type* can_x);
can_error_record_type can_error_type_record_get(can_type* can_x);
uint8_t can_receive_error_counter_get(can_type* can_x);
uint8_t can_transmit_error_counter_get(can_type* can_x);
void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state);
flag_status can_flag_get(can_type* can_x, uint32_t can_flag);
void can_flag_clear(can_type* can_x, uint32_t can_flag);
# 106 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_adc.h" 1
# 86 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_adc.h"
typedef enum
{
  ADC_HCLK_DIV_2 = 0x00,
  ADC_HCLK_DIV_3 = 0x01,
  ADC_HCLK_DIV_4 = 0x02,
  ADC_HCLK_DIV_5 = 0x03,
  ADC_HCLK_DIV_6 = 0x04,
  ADC_HCLK_DIV_7 = 0x05,
  ADC_HCLK_DIV_8 = 0x06,
  ADC_HCLK_DIV_9 = 0x07,
  ADC_HCLK_DIV_10 = 0x08,
  ADC_HCLK_DIV_11 = 0x09,
  ADC_HCLK_DIV_12 = 0x0A,
  ADC_HCLK_DIV_13 = 0x0B,
  ADC_HCLK_DIV_14 = 0x0C,
  ADC_HCLK_DIV_15 = 0x0D,
  ADC_HCLK_DIV_16 = 0x0E,
  ADC_HCLK_DIV_17 = 0x0F
} adc_div_type;




typedef enum
{
  ADC_INDEPENDENT_MODE = 0x00,
  ADC_ORDINARY_SMLT_PREEMPT_SMLT_ONESLAVE_MODE = 0x01,
  ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_ONESLAVE_MODE = 0x02,
  ADC_PREEMPT_SMLT_ONLY_ONESLAVE_MODE = 0x05,
  ADC_ORDINARY_SMLT_ONLY_ONESLAVE_MODE = 0x06,
  ADC_ORDINARY_SHIFT_ONLY_ONESLAVE_MODE = 0x07,
  ADC_PREEMPT_INTERLTRIG_ONLY_ONESLAVE_MODE = 0x09,
  ADC_ORDINARY_SMLT_PREEMPT_SMLT_TWOSLAVE_MODE = 0x11,
  ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_TWOSLAVE_MODE = 0x12,
  ADC_PREEMPT_SMLT_ONLY_TWOSLAVE_MODE = 0x15,
  ADC_ORDINARY_SMLT_ONLY_TWOSLAVE_MODE = 0x16,
  ADC_ORDINARY_SHIFT_ONLY_TWOSLAVE_MODE = 0x17,
  ADC_PREEMPT_INTERLTRIG_ONLY_TWOSLAVE_MODE = 0x19
} adc_combine_mode_type;




typedef enum
{
  ADC_COMMON_DMAMODE_DISABLE = 0x00,
  ADC_COMMON_DMAMODE_1 = 0x01,
  ADC_COMMON_DMAMODE_2 = 0x02,
  ADC_COMMON_DMAMODE_3 = 0x03,
  ADC_COMMON_DMAMODE_4 = 0x04,
  ADC_COMMON_DMAMODE_5 = 0x05
} adc_common_dma_mode_type;




typedef enum
{
  ADC_SAMPLING_INTERVAL_5CYCLES = 0x00,
  ADC_SAMPLING_INTERVAL_6CYCLES = 0x01,
  ADC_SAMPLING_INTERVAL_7CYCLES = 0x02,
  ADC_SAMPLING_INTERVAL_8CYCLES = 0x03,
  ADC_SAMPLING_INTERVAL_9CYCLES = 0x04,
  ADC_SAMPLING_INTERVAL_10CYCLES = 0x05,
  ADC_SAMPLING_INTERVAL_11CYCLES = 0x06,
  ADC_SAMPLING_INTERVAL_12CYCLES = 0x07,
  ADC_SAMPLING_INTERVAL_13CYCLES = 0x08,
  ADC_SAMPLING_INTERVAL_14CYCLES = 0x09,
  ADC_SAMPLING_INTERVAL_15CYCLES = 0x0A,
  ADC_SAMPLING_INTERVAL_16CYCLES = 0x0B,
  ADC_SAMPLING_INTERVAL_17CYCLES = 0x0C,
  ADC_SAMPLING_INTERVAL_18CYCLES = 0x0D,
  ADC_SAMPLING_INTERVAL_19CYCLES = 0x0E,
  ADC_SAMPLING_INTERVAL_20CYCLES = 0x0F
} adc_sampling_interval_type;




typedef enum
{
  ADC_RESOLUTION_12B = 0x00,
  ADC_RESOLUTION_10B = 0x01,
  ADC_RESOLUTION_8B = 0x02,
  ADC_RESOLUTION_6B = 0x03
} adc_resolution_type;




typedef enum
{
  ADC_RIGHT_ALIGNMENT = 0x00,
  ADC_LEFT_ALIGNMENT = 0x01
} adc_data_align_type;




typedef enum
{
  ADC_CHANNEL_0 = 0x00,
  ADC_CHANNEL_1 = 0x01,
  ADC_CHANNEL_2 = 0x02,
  ADC_CHANNEL_3 = 0x03,
  ADC_CHANNEL_4 = 0x04,
  ADC_CHANNEL_5 = 0x05,
  ADC_CHANNEL_6 = 0x06,
  ADC_CHANNEL_7 = 0x07,
  ADC_CHANNEL_8 = 0x08,
  ADC_CHANNEL_9 = 0x09,
  ADC_CHANNEL_10 = 0x0A,
  ADC_CHANNEL_11 = 0x0B,
  ADC_CHANNEL_12 = 0x0C,
  ADC_CHANNEL_13 = 0x0D,
  ADC_CHANNEL_14 = 0x0E,
  ADC_CHANNEL_15 = 0x0F,
  ADC_CHANNEL_16 = 0x10,
  ADC_CHANNEL_17 = 0x11,
  ADC_CHANNEL_18 = 0x12
} adc_channel_select_type;




typedef enum
{
  ADC_SAMPLETIME_2_5 = 0x00,
  ADC_SAMPLETIME_6_5 = 0x01,
  ADC_SAMPLETIME_12_5 = 0x02,
  ADC_SAMPLETIME_24_5 = 0x03,
  ADC_SAMPLETIME_47_5 = 0x04,
  ADC_SAMPLETIME_92_5 = 0x05,
  ADC_SAMPLETIME_247_5 = 0x06,
  ADC_SAMPLETIME_640_5 = 0x07
} adc_sampletime_select_type;




typedef enum
{
  ADC_ORDINARY_TRIG_TMR1CH1 = 0x00,
  ADC_ORDINARY_TRIG_TMR1CH2 = 0x01,
  ADC_ORDINARY_TRIG_TMR1CH3 = 0x02,
  ADC_ORDINARY_TRIG_TMR2CH2 = 0x03,
  ADC_ORDINARY_TRIG_TMR2CH3 = 0x04,
  ADC_ORDINARY_TRIG_TMR2CH4 = 0x05,
  ADC_ORDINARY_TRIG_TMR2TRGOUT = 0x06,
  ADC_ORDINARY_TRIG_TMR3CH1 = 0x07,
  ADC_ORDINARY_TRIG_TMR3TRGOUT = 0x08,
  ADC_ORDINARY_TRIG_TMR4CH4 = 0x09,
  ADC_ORDINARY_TRIG_TMR5CH1 = 0x0A,
  ADC_ORDINARY_TRIG_TMR5CH2 = 0x0B,
  ADC_ORDINARY_TRIG_TMR5CH3 = 0x0C,
  ADC_ORDINARY_TRIG_TMR8CH1 = 0x0D,
  ADC_ORDINARY_TRIG_TMR8TRGOUT = 0x0E,
  ADC_ORDINARY_TRIG_EXINT11 = 0x0F,
  ADC_ORDINARY_TRIG_TMR20TRGOUT = 0x10,
  ADC_ORDINARY_TRIG_TMR20TRGOUT2 = 0x11,
  ADC_ORDINARY_TRIG_TMR20CH1 = 0x12,
  ADC_ORDINARY_TRIG_TMR20CH2 = 0x13,
  ADC_ORDINARY_TRIG_TMR20CH3 = 0x14,
  ADC_ORDINARY_TRIG_TMR8TRGOUT2 = 0x15,
  ADC_ORDINARY_TRIG_TMR1TRGOUT2 = 0x16,
  ADC_ORDINARY_TRIG_TMR4TRGOUT = 0x17,
  ADC_ORDINARY_TRIG_TMR6TRGOUT = 0x18,
  ADC_ORDINARY_TRIG_TMR3CH4 = 0x19,
  ADC_ORDINARY_TRIG_TMR4CH1 = 0x1A,
  ADC_ORDINARY_TRIG_TMR1TRGOUT = 0x1B,
  ADC_ORDINARY_TRIG_TMR2CH1 = 0x1C,
  ADC_ORDINARY_TRIG_TMR7TRGOUT = 0x1E
} adc_ordinary_trig_select_type;




typedef enum
{
  ADC_ORDINARY_TRIG_EDGE_NONE = 0x00,
  ADC_ORDINARY_TRIG_EDGE_RISING = 0x01,
  ADC_ORDINARY_TRIG_EDGE_FALLING = 0x02,
  ADC_ORDINARY_TRIG_EDGE_RISING_FALLING = 0x03
} adc_ordinary_trig_edge_type;




typedef enum
{
  ADC_PREEMPT_TRIG_TMR1CH4 = 0x00,
  ADC_PREEMPT_TRIG_TMR1TRGOUT = 0x01,
  ADC_PREEMPT_TRIG_TMR2CH1 = 0x02,
  ADC_PREEMPT_TRIG_TMR2TRGOUT = 0x03,
  ADC_PREEMPT_TRIG_TMR3CH2 = 0x04,
  ADC_PREEMPT_TRIG_TMR3CH4 = 0x05,
  ADC_PREEMPT_TRIG_TMR4CH1 = 0x06,
  ADC_PREEMPT_TRIG_TMR4CH2 = 0x07,
  ADC_PREEMPT_TRIG_TMR4CH3 = 0x08,
  ADC_PREEMPT_TRIG_TMR4TRGOUT = 0x09,
  ADC_PREEMPT_TRIG_TMR5CH4 = 0x0A,
  ADC_PREEMPT_TRIG_TMR5TRGOUT = 0x0B,
  ADC_PREEMPT_TRIG_TMR8CH2 = 0x0C,
  ADC_PREEMPT_TRIG_TMR8CH3 = 0x0D,
  ADC_PREEMPT_TRIG_TMR8CH4 = 0x0E,
  ADC_PREEMPT_TRIG_EXINT15 = 0x0F,
  ADC_PREEMPT_TRIG_TMR20TRGOUT = 0x10,
  ADC_PREEMPT_TRIG_TMR20TRGOUT2 = 0x11,
  ADC_PREEMPT_TRIG_TMR20CH4 = 0x12,
  ADC_PREEMPT_TRIG_TMR1TRGOUT2 = 0x13,
  ADC_PREEMPT_TRIG_TMR8TRGOUT = 0x14,
  ADC_PREEMPT_TRIG_TMR8TRGOUT2 = 0x15,
  ADC_PREEMPT_TRIG_TMR3CH3 = 0x16,
  ADC_PREEMPT_TRIG_TMR3TRGOUT = 0x17,
  ADC_PREEMPT_TRIG_TMR3CH1 = 0x18,
  ADC_PREEMPT_TRIG_TMR6TRGOUT = 0x19,
  ADC_PREEMPT_TRIG_TMR4CH4 = 0x1A,
  ADC_PREEMPT_TRIG_TMR1CH3 = 0x1B,
  ADC_PREEMPT_TRIG_TMR20CH2 = 0x1C,
  ADC_PREEMPT_TRIG_TMR7TRGOUT = 0x1E
} adc_preempt_trig_select_type;




typedef enum
{
  ADC_PREEMPT_TRIG_EDGE_NONE = 0x00,
  ADC_PREEMPT_TRIG_EDGE_RISING = 0x01,
  ADC_PREEMPT_TRIG_EDGE_FALLING = 0x02,
  ADC_PREEMPT_TRIG_EDGE_RISING_FALLING = 0x03
} adc_preempt_trig_edge_type;




typedef enum
{
  ADC_PREEMPT_CHANNEL_1 = 0x00,
  ADC_PREEMPT_CHANNEL_2 = 0x01,
  ADC_PREEMPT_CHANNEL_3 = 0x02,
  ADC_PREEMPT_CHANNEL_4 = 0x03
} adc_preempt_channel_type;




typedef enum
{
  ADC_VMONITOR_SINGLE_ORDINARY = 0x00800200,
  ADC_VMONITOR_SINGLE_PREEMPT = 0x00400200,
  ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT = 0x00C00200,
  ADC_VMONITOR_ALL_ORDINARY = 0x00800000,
  ADC_VMONITOR_ALL_PREEMPT = 0x00400000,
  ADC_VMONITOR_ALL_ORDINARY_PREEMPT = 0x00C00000,
  ADC_VMONITOR_NONE = 0x00000000
} adc_voltage_monitoring_type;




typedef enum
{
  ADC_OVERSAMPLE_RATIO_2 = 0x00,
  ADC_OVERSAMPLE_RATIO_4 = 0x01,
  ADC_OVERSAMPLE_RATIO_8 = 0x02,
  ADC_OVERSAMPLE_RATIO_16 = 0x03,
  ADC_OVERSAMPLE_RATIO_32 = 0x04,
  ADC_OVERSAMPLE_RATIO_64 = 0x05,
  ADC_OVERSAMPLE_RATIO_128 = 0x06,
  ADC_OVERSAMPLE_RATIO_256 = 0x07
} adc_oversample_ratio_type;




typedef enum
{
  ADC_OVERSAMPLE_SHIFT_0 = 0x00,
  ADC_OVERSAMPLE_SHIFT_1 = 0x01,
  ADC_OVERSAMPLE_SHIFT_2 = 0x02,
  ADC_OVERSAMPLE_SHIFT_3 = 0x03,
  ADC_OVERSAMPLE_SHIFT_4 = 0x04,
  ADC_OVERSAMPLE_SHIFT_5 = 0x05,
  ADC_OVERSAMPLE_SHIFT_6 = 0x06,
  ADC_OVERSAMPLE_SHIFT_7 = 0x07,
  ADC_OVERSAMPLE_SHIFT_8 = 0x08
} adc_oversample_shift_type;




typedef enum
{
  ADC_OVERSAMPLE_CONTINUE = 0x00,
  ADC_OVERSAMPLE_RESTART = 0x01
} adc_ordinary_oversample_restart_type;




typedef struct
{
  adc_combine_mode_type combine_mode;
  adc_div_type div;
  adc_common_dma_mode_type common_dma_mode;
  confirm_state common_dma_request_repeat_state;
  adc_sampling_interval_type sampling_interval;
  confirm_state tempervintrv_state;
  confirm_state vbat_state;
} adc_common_config_type;




typedef struct
{
  confirm_state sequence_mode;
  confirm_state repeat_mode;
  adc_data_align_type data_align;
  uint8_t ordinary_channel_length;
} adc_base_config_type;




typedef struct
{




  union
  {
    volatile uint32_t sts;
    struct
    {
      volatile uint32_t vmor : 1;
      volatile uint32_t occe : 1;
      volatile uint32_t pcce : 1;
      volatile uint32_t pccs : 1;
      volatile uint32_t occs : 1;
      volatile uint32_t occo : 1;
      volatile uint32_t rdy : 1;
      volatile uint32_t reserved1 : 25;
    } sts_bit;
  };




  union
  {
    volatile uint32_t ctrl1;
    struct
    {
      volatile uint32_t vmcsel : 5;
      volatile uint32_t occeien : 1;
      volatile uint32_t vmorien : 1;
      volatile uint32_t pcceien : 1;
      volatile uint32_t sqen : 1;
      volatile uint32_t vmsgen : 1;
      volatile uint32_t pcautoen : 1;
      volatile uint32_t ocpen : 1;
      volatile uint32_t pcpen : 1;
      volatile uint32_t ocpcnt : 3;
      volatile uint32_t reserved1 : 6;
      volatile uint32_t pcvmen : 1;
      volatile uint32_t ocvmen : 1;
      volatile uint32_t crsel : 2;
      volatile uint32_t occoien : 1;
      volatile uint32_t reserved2 : 5;
    } ctrl1_bit;
  };




  union
  {
    volatile uint32_t ctrl2;
    struct
    {
      volatile uint32_t adcen : 1;
      volatile uint32_t rpen : 1;
      volatile uint32_t adcal : 1;
      volatile uint32_t adcalinit : 1;
      volatile uint32_t adabrt : 1;
      volatile uint32_t reserved1 : 3;
      volatile uint32_t ocdmaen : 1;
      volatile uint32_t ocdrcen : 1;
      volatile uint32_t eocsfen : 1;
      volatile uint32_t dtalign : 1;
      volatile uint32_t reserved2 : 4;
      volatile uint32_t pctesel_l : 4;
      volatile uint32_t pcete : 2;
      volatile uint32_t pcswtrg : 1;
      volatile uint32_t pctesel_h : 1;
      volatile uint32_t octesel_l : 4;
      volatile uint32_t ocete : 2;
      volatile uint32_t ocswtrg : 1;
      volatile uint32_t octesel_h : 1;
    } ctrl2_bit;
  };




  union
  {
    volatile uint32_t spt1;
    struct
    {
      volatile uint32_t cspt10 : 3;
      volatile uint32_t cspt11 : 3;
      volatile uint32_t cspt12 : 3;
      volatile uint32_t cspt13 : 3;
      volatile uint32_t cspt14 : 3;
      volatile uint32_t cspt15 : 3;
      volatile uint32_t cspt16 : 3;
      volatile uint32_t cspt17 : 3;
      volatile uint32_t cspt18 : 3;
      volatile uint32_t reserved1 : 5;
    } spt1_bit;
  };




  union
  {
    volatile uint32_t spt2;
    struct
    {
      volatile uint32_t cspt0 : 3;
      volatile uint32_t cspt1 : 3;
      volatile uint32_t cspt2 : 3;
      volatile uint32_t cspt3 : 3;
      volatile uint32_t cspt4 : 3;
      volatile uint32_t cspt5 : 3;
      volatile uint32_t cspt6 : 3;
      volatile uint32_t cspt7 : 3;
      volatile uint32_t cspt8 : 3;
      volatile uint32_t cspt9 : 3;
      volatile uint32_t reserved1 : 2;
    } spt2_bit;
  };




  union
  {
    volatile uint32_t pcdto1;
    struct
    {
      volatile uint32_t pcdto1 : 12;
      volatile uint32_t reserved1 : 20;
    } pcdto1_bit;
  };




  union
  {
    volatile uint32_t pcdto2;
    struct
    {
      volatile uint32_t pcdto2 : 12;
      volatile uint32_t reserved1 : 20;
    } pcdto2_bit;
  };




  union
  {
    volatile uint32_t pcdto3;
    struct
    {
      volatile uint32_t pcdto3 : 12;
      volatile uint32_t reserved1 : 20;
    } pcdto3_bit;
  };




  union
  {
    volatile uint32_t pcdto4;
    struct
    {
      volatile uint32_t pcdto4 : 12;
      volatile uint32_t reserved1 : 20;
    } pcdto4_bit;
  };




  union
  {
    volatile uint32_t vmhb;
    struct
    {
      volatile uint32_t vmhb : 12;
      volatile uint32_t reserved1 : 20;
    } vmhb_bit;
  };




  union
  {
    volatile uint32_t vmlb;
    struct
    {
      volatile uint32_t vmlb : 12;
      volatile uint32_t reserved1 : 20;
    } vmlb_bit;
  };




  union
  {
    volatile uint32_t osq1;
    struct
    {
      volatile uint32_t osn13 : 5;
      volatile uint32_t osn14 : 5;
      volatile uint32_t osn15 : 5;
      volatile uint32_t osn16 : 5;
      volatile uint32_t oclen : 4;
      volatile uint32_t reserved1 : 8;
    } osq1_bit;
  };




  union
  {
    volatile uint32_t osq2;
    struct
    {
      volatile uint32_t osn7 : 5;
      volatile uint32_t osn8 : 5;
      volatile uint32_t osn9 : 5;
      volatile uint32_t osn10 : 5;
      volatile uint32_t osn11 : 5;
      volatile uint32_t osn12 : 5;
      volatile uint32_t reserved1 : 2;
    } osq2_bit;
  };




  union
  {
    volatile uint32_t osq3;
    struct
    {
      volatile uint32_t osn1 : 5;
      volatile uint32_t osn2 : 5;
      volatile uint32_t osn3 : 5;
      volatile uint32_t osn4 : 5;
      volatile uint32_t osn5 : 5;
      volatile uint32_t osn6 : 5;
      volatile uint32_t reserved1 : 2;
    } osq3_bit;
  };




  union
  {
    volatile uint32_t psq;
    struct
    {
      volatile uint32_t psn1 : 5;
      volatile uint32_t psn2 : 5;
      volatile uint32_t psn3 : 5;
      volatile uint32_t psn4 : 5;
      volatile uint32_t pclen : 2;
      volatile uint32_t reserved1 : 10;
    } psq_bit;
  };




  union
  {
    volatile uint32_t pdt1;
    struct
    {
      volatile uint32_t pdt1 : 16;
      volatile uint32_t reserved1 : 16;
    } pdt1_bit;
  };




  union
  {
    volatile uint32_t pdt2;
    struct
    {
      volatile uint32_t pdt2 : 16;
      volatile uint32_t reserved1 : 16;
    } pdt2_bit;
  };




  union
  {
    volatile uint32_t pdt3;
    struct
    {
      volatile uint32_t pdt3 : 16;
      volatile uint32_t reserved1 : 16;
    } pdt3_bit;
  };




  union
  {
    volatile uint32_t pdt4;
    struct
    {
      volatile uint32_t pdt4 : 16;
      volatile uint32_t reserved1 : 16;
    } pdt4_bit;
  };




  union
  {
    volatile uint32_t odt;
    struct
    {
      volatile uint32_t odt : 16;
      volatile uint32_t reserved1 : 16;
    } odt_bit;
  };

  volatile uint32_t reserved1[12];




  union
  {
    volatile uint32_t ovsp;
    struct
    {
      volatile uint32_t oosen : 1;
      volatile uint32_t posen : 1;
      volatile uint32_t osrsel : 3;
      volatile uint32_t osssel : 4;
      volatile uint32_t oostren : 1;
      volatile uint32_t oosrsel : 1;
      volatile uint32_t reserved1 : 21;
    } ovsp_bit;
  };

  volatile uint32_t reserved2[12];




  union
  {
    volatile uint32_t calval;
    struct
    {
      volatile uint32_t calval : 7;
      volatile uint32_t reserved1 : 25;
    } calval_bit;
  };
} adc_type;




typedef struct
{




  union
  {
    volatile uint32_t csts;
    struct
    {
      volatile uint32_t vmor1 : 1;
      volatile uint32_t occe1 : 1;
      volatile uint32_t pcce1 : 1;
      volatile uint32_t pccs1 : 1;
      volatile uint32_t occs1 : 1;
      volatile uint32_t occo1 : 1;
      volatile uint32_t rdy1 : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t vmor2 : 1;
      volatile uint32_t occe2 : 1;
      volatile uint32_t pcce2 : 1;
      volatile uint32_t pccs2 : 1;
      volatile uint32_t occs2 : 1;
      volatile uint32_t occo2 : 1;
      volatile uint32_t rdy2 : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t vmor3 : 1;
      volatile uint32_t occe3 : 1;
      volatile uint32_t pcce3 : 1;
      volatile uint32_t pccs3 : 1;
      volatile uint32_t occs3 : 1;
      volatile uint32_t occo3 : 1;
      volatile uint32_t rdy3 : 1;
      volatile uint32_t reserved3 : 9;
    } csts_bit;
  };




  union
  {
    volatile uint32_t cctrl;
    struct
    {
      volatile uint32_t mssel : 5;
      volatile uint32_t reserved1 : 3;
      volatile uint32_t asisel : 4;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t msdrcen : 1;
      volatile uint32_t msdmasel_l : 2;
      volatile uint32_t adcdiv : 4;
      volatile uint32_t reserved3 : 2;
      volatile uint32_t vbaten : 1;
      volatile uint32_t itsrven : 1;
      volatile uint32_t reserved4 : 4;
      volatile uint32_t msdmasel_h : 1;
      volatile uint32_t reserved5 : 3;
    } cctrl_bit;
  };




  union
  {
    volatile uint32_t codt;
    struct
    {
      volatile uint32_t codtl : 16;
      volatile uint32_t codth : 16;
    } codt_bit;
  };
} adccom_type;
# 875 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_adc.h"
void adc_reset(void);
void adc_enable(adc_type *adc_x, confirm_state new_state);
void adc_base_default_para_init(adc_base_config_type *adc_base_struct);
void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct);
void adc_common_default_para_init(adc_common_config_type *adc_common_struct);
void adc_common_config(adc_common_config_type *adc_common_struct);
void adc_resolution_set(adc_type *adc_x, adc_resolution_type resolution);
void adc_voltage_battery_enable(confirm_state new_state);
void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state);
void adc_dma_request_repeat_enable(adc_type *adc_x, confirm_state new_state);
void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state);
void adc_calibration_value_set(adc_type *adc_x, uint8_t adc_calibration_value);
void adc_calibration_init(adc_type *adc_x);
flag_status adc_calibration_init_status_get(adc_type *adc_x);
void adc_calibration_start(adc_type *adc_x);
flag_status adc_calibration_status_get(adc_type *adc_x);
void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring);
void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold);
void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel);
void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght);
void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, adc_ordinary_trig_edge_type adc_ordinary_trig_edge);
void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, adc_preempt_trig_edge_type adc_preempt_trig_edge);
void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value);
void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count);
void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state);
void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state);
void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state);
void adc_conversion_stop(adc_type *adc_x);
flag_status adc_conversion_stop_status_get(adc_type *adc_x);
void adc_occe_each_conversion_enable(adc_type *adc_x, confirm_state new_state);
void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x);
void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x);
uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x);
uint32_t adc_combine_ordinary_conversion_data_get(void);
uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel);
flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag);
void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag);
void adc_ordinary_oversample_enable(adc_type *adc_x, confirm_state new_state);
void adc_preempt_oversample_enable(adc_type *adc_x, confirm_state new_state);
void adc_oversample_ratio_shift_set(adc_type *adc_x, adc_oversample_ratio_type adc_oversample_ratio, adc_oversample_shift_type adc_oversample_shift);
void adc_ordinary_oversample_trig_enable(adc_type *adc_x, confirm_state new_state);
void adc_ordinary_oversample_restart_set(adc_type *adc_x, adc_ordinary_oversample_restart_type adc_ordinary_oversample_restart);
# 109 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_dac.h" 1
# 57 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_dac.h"
typedef enum
{
  DAC1_SELECT = 0x01,
  DAC2_SELECT = 0x02
} dac_select_type;




typedef enum
{
  DAC_TMR6_TRGOUT_EVENT = 0x00,
  DAC_TMR8_TRGOUT_EVENT = 0x01,
  DAC_TMR7_TRGOUT_EVENT = 0x02,
  DAC_TMR5_TRGOUT_EVENT = 0x03,
  DAC_TMR2_TRGOUT_EVENT = 0x04,
  DAC_TMR4_TRGOUT_EVENT = 0x05,
  DAC_EXTERNAL_INTERRUPT_LINE_9 = 0x06,
  DAC_SOFTWARE_TRIGGER = 0x07
} dac_trigger_type;




typedef enum
{
  DAC_WAVE_GENERATE_NONE = 0x00,
  DAC_WAVE_GENERATE_NOISE = 0x01,
  DAC_WAVE_GENERATE_TRIANGLE = 0x02
} dac_wave_type;




typedef enum
{
  DAC_LSFR_BIT0_AMPLITUDE_1 = 0x00,
  DAC_LSFR_BIT10_AMPLITUDE_3 = 0x01,
  DAC_LSFR_BIT20_AMPLITUDE_7 = 0x02,
  DAC_LSFR_BIT30_AMPLITUDE_15 = 0x03,
  DAC_LSFR_BIT40_AMPLITUDE_31 = 0x04,
  DAC_LSFR_BIT50_AMPLITUDE_63 = 0x05,
  DAC_LSFR_BIT60_AMPLITUDE_127 = 0x06,
  DAC_LSFR_BIT70_AMPLITUDE_255 = 0x07,
  DAC_LSFR_BIT80_AMPLITUDE_511 = 0x08,
  DAC_LSFR_BIT90_AMPLITUDE_1023 = 0x09,
  DAC_LSFR_BITA0_AMPLITUDE_2047 = 0x0A,
  DAC_LSFR_BITB0_AMPLITUDE_4095 = 0x0B
} dac_mask_amplitude_type;




typedef enum
{
  DAC1_12BIT_RIGHT = 0x40007408,
  DAC1_12BIT_LEFT = 0x4000740C,
  DAC1_8BIT_RIGHT = 0x40007410
} dac1_aligned_data_type;




typedef enum
{
  DAC2_12BIT_RIGHT = 0x40007414,
  DAC2_12BIT_LEFT = 0x40007418,
  DAC2_8BIT_RIGHT = 0x4000741C
} dac2_aligned_data_type;




typedef enum
{
  DAC_DUAL_12BIT_RIGHT = 0x40007420,
  DAC_DUAL_12BIT_LEFT = 0x40007424,
  DAC_DUAL_8BIT_RIGHT = 0x40007428
} dac_dual_data_type;




typedef struct
{



  union
  {
    volatile uint32_t ctrl;
    struct
    {
      volatile uint32_t d1en : 1;
      volatile uint32_t d1obdis : 1;
      volatile uint32_t d1trgen : 1;
      volatile uint32_t d1trgsel : 3;
      volatile uint32_t d1nm : 2;
      volatile uint32_t d1nbsel : 4;
      volatile uint32_t d1dmaen : 1;
      volatile uint32_t d1dmaudrien : 1;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t d2en : 1;
      volatile uint32_t d2obdis : 1;
      volatile uint32_t d2trgen : 1;
      volatile uint32_t d2trgsel : 3;
      volatile uint32_t d2nm : 2;
      volatile uint32_t d2nbsel : 4;
      volatile uint32_t d2dmaen : 1;
      volatile uint32_t d2dmaudrien : 1;
      volatile uint32_t reserved2 : 2;
    } ctrl_bit;
  };




  union
  {
    volatile uint32_t swtrg;
    struct
    {
      volatile uint32_t d1swtrg : 1;
      volatile uint32_t d2swtrg : 1;
      volatile uint32_t reserved1 : 30;
    } swtrg_bit;
  };




  union
  {
    volatile uint32_t d1dth12r;
    struct
    {
      volatile uint32_t d1dt12r : 12;
      volatile uint32_t reserved1 : 20;
    } d1dth12r_bit;
  };




  union
  {
    volatile uint32_t d1dth12l;
    struct
    {
      volatile uint32_t d1dt12l : 12;
      volatile uint32_t reserved1 : 20;
    } d1dth12l_bit;
  };




  union
  {
    volatile uint32_t d1dth8r;
    struct
    {
      volatile uint32_t d1dt8r : 8;
      volatile uint32_t reserved1 : 24;
    } d1dth8r_bit;
  };




  union
  {
    volatile uint32_t d2dth12r;
    struct
    {
      volatile uint32_t d2dt12r : 12;
      volatile uint32_t reserved1 : 20;
    } d2dth12r_bit;
  };




  union
  {
    volatile uint32_t d2dth12l;
    struct
    {
      volatile uint32_t d2dt12l : 12;
      volatile uint32_t reserved1 : 20;
    } d2dth12l_bit;
  };




  union
  {
    volatile uint32_t d2dth8r;
    struct
    {
      volatile uint32_t d2dt8r : 8;
      volatile uint32_t reserved1 : 24;
    } d2dth8r_bit;
  };




  union
  {
    volatile uint32_t ddth12r;
    struct
    {
      volatile uint32_t dd1dt12r : 12;
      volatile uint32_t reserved1 : 4;
      volatile uint32_t dd2dt12r : 12;
      volatile uint32_t reserved2 : 4;
    } ddth12r_bit;
  };




  union
  {
    volatile uint32_t ddth12l;
    struct
    {
      volatile uint32_t reserved1 : 4;
      volatile uint32_t dd1dt12l : 12;
      volatile uint32_t reserved2 : 4;
      volatile uint32_t dd2dt12l : 12;
    } ddth12l_bit;
  };




  union
  {
    volatile uint32_t ddth8r;
    struct
    {
      volatile uint32_t dd1dt8r : 8;
      volatile uint32_t dd2dt8r : 8;
      volatile uint32_t reserved1 : 16;
    } ddth8r_bit;
  };




  union
  {
    volatile uint32_t d1odt;
    struct
    {
      volatile uint32_t d1odt : 12;
      volatile uint32_t reserved1 : 20;
    } d1odt_bit;
  };




  union
  {
    volatile uint32_t d2odt;
    struct
    {
      volatile uint32_t d2odt : 12;
      volatile uint32_t reserved1 : 20;
    } d2odt_bit;
  };




  union
  {
    volatile uint32_t sts;
    struct
    {
      volatile uint32_t reserved1 : 13;
      volatile uint32_t d1dmaudrf : 1;
      volatile uint32_t reserved2 : 15;
      volatile uint32_t d2dmaudrf : 1;
      volatile uint32_t reserved3 : 2;
    } sts_bit;
  };
} dac_type;
# 360 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_dac.h"
void dac_reset(void);
void dac_enable(dac_select_type dac_select, confirm_state new_state);
void dac_output_buffer_enable(dac_select_type dac_select, confirm_state new_state);
void dac_trigger_enable(dac_select_type dac_select, confirm_state new_state);
void dac_trigger_select(dac_select_type dac_select, dac_trigger_type dac_trigger_source);
void dac_software_trigger_generate(dac_select_type dac_select);
void dac_dual_software_trigger_generate(void);
void dac_wave_generate(dac_select_type dac_select, dac_wave_type dac_wave);
void dac_mask_amplitude_select(dac_select_type dac_select, dac_mask_amplitude_type dac_mask_amplitude);
void dac_dma_enable(dac_select_type dac_select, confirm_state new_state);
uint16_t dac_data_output_get(dac_select_type dac_select);
void dac_1_data_set(dac1_aligned_data_type dac1_aligned, uint16_t dac1_data);
void dac_2_data_set(dac2_aligned_data_type dac2_aligned, uint16_t dac2_data);
void dac_dual_data_set(dac_dual_data_type dac_dual, uint16_t data1, uint16_t data2);
void dac_udr_enable(dac_select_type dac_select, confirm_state new_state);
flag_status dac_udr_flag_get(dac_select_type dac_select);
void dac_udr_flag_clear(dac_select_type dac_select);
# 112 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_spi.h" 1
# 88 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_spi.h"
typedef enum
{
  SPI_FRAME_8BIT = 0x00,
  SPI_FRAME_16BIT = 0x01
} spi_frame_bit_num_type;




typedef enum
{
  SPI_MODE_SLAVE = 0x00,
  SPI_MODE_MASTER = 0x01
} spi_master_slave_mode_type;




typedef enum
{
  SPI_CLOCK_POLARITY_LOW = 0x00,
  SPI_CLOCK_POLARITY_HIGH = 0x01
} spi_clock_polarity_type;




typedef enum
{
  SPI_CLOCK_PHASE_1EDGE = 0x00,
  SPI_CLOCK_PHASE_2EDGE = 0x01
} spi_clock_phase_type;




typedef enum
{
  SPI_CS_HARDWARE_MODE = 0x00,
  SPI_CS_SOFTWARE_MODE = 0x01
} spi_cs_mode_type;




typedef enum
{
  SPI_MCLK_DIV_2 = 0x00,
  SPI_MCLK_DIV_3 = 0x0A,
  SPI_MCLK_DIV_4 = 0x01,
  SPI_MCLK_DIV_8 = 0x02,
  SPI_MCLK_DIV_16 = 0x03,
  SPI_MCLK_DIV_32 = 0x04,
  SPI_MCLK_DIV_64 = 0x05,
  SPI_MCLK_DIV_128 = 0x06,
  SPI_MCLK_DIV_256 = 0x07,
  SPI_MCLK_DIV_512 = 0x08,
  SPI_MCLK_DIV_1024 = 0x09
} spi_mclk_freq_div_type;




typedef enum
{
  SPI_FIRST_BIT_MSB = 0x00,
  SPI_FIRST_BIT_LSB = 0x01
} spi_first_bit_type;




typedef enum
{
  SPI_TRANSMIT_FULL_DUPLEX = 0x00,
  SPI_TRANSMIT_SIMPLEX_RX = 0x01,
  SPI_TRANSMIT_HALF_DUPLEX_RX = 0x02,
  SPI_TRANSMIT_HALF_DUPLEX_TX = 0x03
} spi_transmission_mode_type;




typedef enum
{
  SPI_CRC_RX = 0x0014,
  SPI_CRC_TX = 0x0018
} spi_crc_direction_type;




typedef enum
{
  SPI_HALF_DUPLEX_DIRECTION_RX = 0x00,
  SPI_HALF_DUPLEX_DIRECTION_TX = 0x01
} spi_half_duplex_direction_type;




typedef enum
{
  SPI_SWCS_INTERNAL_LEVEL_LOW = 0x00,
  SPI_SWCS_INTERNAL_LEVEL_HIGHT = 0x01
} spi_software_cs_level_type;




typedef enum
{
  I2S_AUDIO_PROTOCOL_PHILLIPS = 0x00,
  I2S_AUDIO_PROTOCOL_MSB = 0x01,
  I2S_AUDIO_PROTOCOL_LSB = 0x02,
  I2S_AUDIO_PROTOCOL_PCM_SHORT = 0x03,
  I2S_AUDIO_PROTOCOL_PCM_LONG = 0x04
} i2s_audio_protocol_type;




typedef enum
{
  I2S_AUDIO_FREQUENCY_DEFAULT = 2,
  I2S_AUDIO_FREQUENCY_8K = 8000,
  I2S_AUDIO_FREQUENCY_11_025K = 11025,
  I2S_AUDIO_FREQUENCY_16K = 16000,
  I2S_AUDIO_FREQUENCY_22_05K = 22050,
  I2S_AUDIO_FREQUENCY_32K = 32000,
  I2S_AUDIO_FREQUENCY_44_1K = 44100,
  I2S_AUDIO_FREQUENCY_48K = 48000,
  I2S_AUDIO_FREQUENCY_96K = 96000,
  I2S_AUDIO_FREQUENCY_192K = 192000
} i2s_audio_sampling_freq_type;




typedef enum
{
  I2S_DATA_16BIT_CHANNEL_16BIT = 0x01,
  I2S_DATA_16BIT_CHANNEL_32BIT = 0x02,
  I2S_DATA_24BIT_CHANNEL_32BIT = 0x03,
  I2S_DATA_32BIT_CHANNEL_32BIT = 0x04
} i2s_data_channel_format_type;




typedef enum
{
  I2S_MODE_SLAVE_TX = 0x00,
  I2S_MODE_SLAVE_RX = 0x01,
  I2S_MODE_MASTER_TX = 0x02,
  I2S_MODE_MASTER_RX = 0x03
} i2s_operation_mode_type;




typedef enum
{
  I2S_CLOCK_POLARITY_LOW = 0x00,
  I2S_CLOCK_POLARITY_HIGH = 0x01
} i2s_clock_polarity_type;




typedef struct
{
  spi_transmission_mode_type transmission_mode;
  spi_master_slave_mode_type master_slave_mode;
  spi_mclk_freq_div_type mclk_freq_division;
  spi_first_bit_type first_bit_transmission;
  spi_frame_bit_num_type frame_bit_num;
  spi_clock_polarity_type clock_polarity;
  spi_clock_phase_type clock_phase;
  spi_cs_mode_type cs_mode_selection;
} spi_init_type;




typedef struct
{
  i2s_operation_mode_type operation_mode;
  i2s_audio_protocol_type audio_protocol;
  i2s_audio_sampling_freq_type audio_sampling_freq;
  i2s_data_channel_format_type data_channel_format;
  i2s_clock_polarity_type clock_polarity;
  confirm_state mclk_output_enable;
} i2s_init_type;




typedef struct
{




  union
  {
    volatile uint32_t ctrl1;
    struct
    {
      volatile uint32_t clkpha : 1;
      volatile uint32_t clkpol : 1;
      volatile uint32_t msten : 1;
      volatile uint32_t mdiv_l : 3;
      volatile uint32_t spien : 1;
      volatile uint32_t ltf : 1;
      volatile uint32_t swcsil : 1;
      volatile uint32_t swcsen : 1;
      volatile uint32_t ora : 1;
      volatile uint32_t fbn : 1;
      volatile uint32_t ntc : 1;
      volatile uint32_t ccen : 1;
      volatile uint32_t slbtd : 1;
      volatile uint32_t slben : 1;
      volatile uint32_t reserved1 : 16;
    } ctrl1_bit;
  };




  union
  {
    volatile uint32_t ctrl2;
    struct
    {
      volatile uint32_t dmaren : 1;
      volatile uint32_t dmaten : 1;
      volatile uint32_t hwcsoe : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t tien : 1;
      volatile uint32_t errie : 1;
      volatile uint32_t rdbfie : 1;
      volatile uint32_t tdbeie : 1;
      volatile uint32_t mdiv_h : 1;
      volatile uint32_t mdiv3en : 1;
      volatile uint32_t reserved2 : 22;
    } ctrl2_bit;
  };




  union
  {
    volatile uint32_t sts;
    struct
    {
      volatile uint32_t rdbf : 1;
      volatile uint32_t tdbe : 1;
      volatile uint32_t acs : 1;
      volatile uint32_t tuerr : 1;
      volatile uint32_t ccerr : 1;
      volatile uint32_t mmerr : 1;
      volatile uint32_t roerr : 1;
      volatile uint32_t bf : 1;
      volatile uint32_t cspas : 1;
      volatile uint32_t reserved1 : 23;
    } sts_bit;
  };




  union
  {
    volatile uint32_t dt;
    struct
    {
      volatile uint32_t dt : 16;
      volatile uint32_t reserved1 : 16;
    } dt_bit;
  };




  union
  {
    volatile uint32_t cpoly;
    struct
    {
      volatile uint32_t cpoly : 16;
      volatile uint32_t reserved1 : 16;
    } cpoly_bit;
  };




  union
  {
    volatile uint32_t rcrc;
    struct
    {
      volatile uint32_t rcrc : 16;
      volatile uint32_t reserved1 : 16;
    } rcrc_bit;
  };




  union
  {
    volatile uint32_t tcrc;
    struct
    {
      volatile uint32_t tcrc : 16;
      volatile uint32_t reserved1 : 16;
    } tcrc_bit;
  };




  union
  {
    volatile uint32_t i2sctrl;
    struct
    {
      volatile uint32_t i2scbn : 1;
      volatile uint32_t i2sdbn : 2;
      volatile uint32_t i2sclkpol : 1;
      volatile uint32_t stdsel : 2;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t pcmfssel : 1;
      volatile uint32_t opersel : 2;
      volatile uint32_t i2sen : 1;
      volatile uint32_t i2smsel : 1;
      volatile uint32_t reserved2 : 20;
    } i2sctrl_bit;
  };




  union
  {
    volatile uint32_t i2sclk;
    struct
    {
      volatile uint32_t i2sdiv_l : 8;
      volatile uint32_t i2sodd : 1;
      volatile uint32_t i2smclkoe : 1;
      volatile uint32_t i2sdiv_h : 2;
      volatile uint32_t reserved1 : 20;
    } i2sclk_bit;
  };

} spi_type;
# 464 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_spi.h"
void spi_i2s_reset(spi_type *spi_x);
void spi_default_para_init(spi_init_type* spi_init_struct);
void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct);
void spi_ti_mode_enable(spi_type* spi_x, confirm_state new_state);
void spi_crc_next_transmit(spi_type* spi_x);
void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly);
uint16_t spi_crc_polynomial_get(spi_type* spi_x);
void spi_crc_enable(spi_type* spi_x, confirm_state new_state);
uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction);
void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state);
void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level);
void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num);
void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction);
void spi_enable(spi_type* spi_x, confirm_state new_state);
void i2s_default_para_init(i2s_init_type* i2s_init_struct);
void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct);
void i2s_enable(spi_type* spi_x, confirm_state new_state);
void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state);
void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state);
void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state);
void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data);
uint16_t spi_i2s_data_receive(spi_type* spi_x);
flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag);
# 115 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_dma.h" 1
# 150 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_dma.h"
typedef enum
{
  DMA_DIR_PERIPHERAL_TO_MEMORY = 0x0000,
  DMA_DIR_MEMORY_TO_PERIPHERAL = 0x0010,
  DMA_DIR_MEMORY_TO_MEMORY = 0x4000
} dma_dir_type;




typedef enum
{
  DMA_PERIPHERAL_DATA_WIDTH_BYTE = 0x00,
  DMA_PERIPHERAL_DATA_WIDTH_HALFWORD = 0x01,
  DMA_PERIPHERAL_DATA_WIDTH_WORD = 0x02
} dma_peripheral_data_size_type;




typedef enum
{
  DMA_MEMORY_DATA_WIDTH_BYTE = 0x00,
  DMA_MEMORY_DATA_WIDTH_HALFWORD = 0x01,
  DMA_MEMORY_DATA_WIDTH_WORD = 0x02
} dma_memory_data_size_type;




typedef enum
{
  DMA_PRIORITY_LOW = 0x00,
  DMA_PRIORITY_MEDIUM = 0x01,
  DMA_PRIORITY_HIGH = 0x02,
  DMA_PRIORITY_VERY_HIGH = 0x03
} dma_priority_level_type;




typedef enum
{
  DMAMUX_DMAREQ_ID_REQ_G1 = 0x01,
  DMAMUX_DMAREQ_ID_REQ_G2 = 0x02,
  DMAMUX_DMAREQ_ID_REQ_G3 = 0x03,
  DMAMUX_DMAREQ_ID_REQ_G4 = 0x04,
  DMAMUX_DMAREQ_ID_ADC1 = 0x05,
  DMAMUX_DMAREQ_ID_ADC2 = 0x24,
  DMAMUX_DMAREQ_ID_ADC3 = 0x25,
  DMAMUX_DMAREQ_ID_DAC1 = 0x06,
  DMAMUX_DMAREQ_ID_DAC2 = 0x29,
  DMAMUX_DMAREQ_ID_TMR6_OVERFLOW = 0x08,
  DMAMUX_DMAREQ_ID_TMR7_OVERFLOW = 0x09,
  DMAMUX_DMAREQ_ID_SPI1_RX = 0x0A,
  DMAMUX_DMAREQ_ID_SPI1_TX = 0x0B,
  DMAMUX_DMAREQ_ID_SPI2_RX = 0x0C,
  DMAMUX_DMAREQ_ID_SPI2_TX = 0x0D,
  DMAMUX_DMAREQ_ID_SPI3_RX = 0x0E,
  DMAMUX_DMAREQ_ID_SPI3_TX = 0x0F,
  DMAMUX_DMAREQ_ID_SPI4_RX = 0x6A,
  DMAMUX_DMAREQ_ID_SPI4_TX = 0x6B,
  DMAMUX_DMAREQ_ID_I2S2_EXT_RX = 0x6E,
  DMAMUX_DMAREQ_ID_I2S2_EXT_TX = 0x6F,
  DMAMUX_DMAREQ_ID_I2S3_EXT_RX = 0x70,
  DMAMUX_DMAREQ_ID_I2S3_EXT_TX = 0x71,
  DMAMUX_DMAREQ_ID_I2C1_RX = 0x10,
  DMAMUX_DMAREQ_ID_I2C1_TX = 0x11,
  DMAMUX_DMAREQ_ID_I2C2_RX = 0x12,
  DMAMUX_DMAREQ_ID_I2C2_TX = 0x13,
  DMAMUX_DMAREQ_ID_I2C3_RX = 0x14,
  DMAMUX_DMAREQ_ID_I2C3_TX = 0x15,
  DMAMUX_DMAREQ_ID_USART1_RX = 0x18,
  DMAMUX_DMAREQ_ID_USART1_TX = 0x19,
  DMAMUX_DMAREQ_ID_USART2_RX = 0x1A,
  DMAMUX_DMAREQ_ID_USART2_TX = 0x1B,
  DMAMUX_DMAREQ_ID_USART3_RX = 0x1C,
  DMAMUX_DMAREQ_ID_USART3_TX = 0x1D,
  DMAMUX_DMAREQ_ID_UART4_RX = 0x1E,
  DMAMUX_DMAREQ_ID_UART4_TX = 0x1F,
  DMAMUX_DMAREQ_ID_UART5_RX = 0x20,
  DMAMUX_DMAREQ_ID_UART5_TX = 0x21,
  DMAMUX_DMAREQ_ID_USART6_RX = 0x72,
  DMAMUX_DMAREQ_ID_USART6_TX = 0x73,
  DMAMUX_DMAREQ_ID_UART7_RX = 0x74,
  DMAMUX_DMAREQ_ID_UART7_TX = 0x75,
  DMAMUX_DMAREQ_ID_UART8_RX = 0x76,
  DMAMUX_DMAREQ_ID_UART8_TX = 0x77,
  DMAMUX_DMAREQ_ID_SDIO1 = 0x27,
  DMAMUX_DMAREQ_ID_SDIO2 = 0x67,
  DMAMUX_DMAREQ_ID_QSPI1 = 0x28,
  DMAMUX_DMAREQ_ID_QSPI2 = 0x68,
  DMAMUX_DMAREQ_ID_TMR1_CH1 = 0x2A,
  DMAMUX_DMAREQ_ID_TMR1_CH2 = 0x2B,
  DMAMUX_DMAREQ_ID_TMR1_CH3 = 0x2C,
  DMAMUX_DMAREQ_ID_TMR1_CH4 = 0x2D,
  DMAMUX_DMAREQ_ID_TMR1_OVERFLOW = 0x2E,
  DMAMUX_DMAREQ_ID_TMR1_TRIG = 0x2F,
  DMAMUX_DMAREQ_ID_TMR1_HALL = 0x30,
  DMAMUX_DMAREQ_ID_TMR8_CH1 = 0x31,
  DMAMUX_DMAREQ_ID_TMR8_CH2 = 0x32,
  DMAMUX_DMAREQ_ID_TMR8_CH3 = 0x33,
  DMAMUX_DMAREQ_ID_TMR8_CH4 = 0x34,
  DMAMUX_DMAREQ_ID_TMR8_OVERFLOW = 0x35,
  DMAMUX_DMAREQ_ID_TMR8_TRIG = 0x36,
  DMAMUX_DMAREQ_ID_TMR8_HALL = 0x37,
  DMAMUX_DMAREQ_ID_TMR2_CH1 = 0x38,
  DMAMUX_DMAREQ_ID_TMR2_CH2 = 0x39,
  DMAMUX_DMAREQ_ID_TMR2_CH3 = 0x3A,
  DMAMUX_DMAREQ_ID_TMR2_CH4 = 0x3B,
  DMAMUX_DMAREQ_ID_TMR2_OVERFLOW = 0x3C,
  DMAMUX_DMAREQ_ID_TMR2_TRIG = 0x7E,
  DMAMUX_DMAREQ_ID_TMR3_CH1 = 0x3D,
  DMAMUX_DMAREQ_ID_TMR3_CH2 = 0x3E,
  DMAMUX_DMAREQ_ID_TMR3_CH3 = 0x3F,
  DMAMUX_DMAREQ_ID_TMR3_CH4 = 0x40,
  DMAMUX_DMAREQ_ID_TMR3_OVERFLOW = 0x41,
  DMAMUX_DMAREQ_ID_TMR3_TRIG = 0x42,
  DMAMUX_DMAREQ_ID_TMR4_CH1 = 0x43,
  DMAMUX_DMAREQ_ID_TMR4_CH2 = 0x44,
  DMAMUX_DMAREQ_ID_TMR4_CH3 = 0x45,
  DMAMUX_DMAREQ_ID_TMR4_CH4 = 0x46,
  DMAMUX_DMAREQ_ID_TMR4_OVERFLOW = 0x47,
  DMAMUX_DMAREQ_ID_TMR4_TRIG = 0x7F,
  DMAMUX_DMAREQ_ID_TMR5_CH1 = 0x48,
  DMAMUX_DMAREQ_ID_TMR5_CH2 = 0x49,
  DMAMUX_DMAREQ_ID_TMR5_CH3 = 0x4A,
  DMAMUX_DMAREQ_ID_TMR5_CH4 = 0x4B,
  DMAMUX_DMAREQ_ID_TMR5_OVERFLOW = 0x4C,
  DMAMUX_DMAREQ_ID_TMR5_TRIG = 0x4D,
  DMAMUX_DMAREQ_ID_TMR20_CH1 = 0x56,
  DMAMUX_DMAREQ_ID_TMR20_CH2 = 0x57,
  DMAMUX_DMAREQ_ID_TMR20_CH3 = 0x58,
  DMAMUX_DMAREQ_ID_TMR20_CH4 = 0x59,
  DMAMUX_DMAREQ_ID_TMR20_OVERFLOW = 0x5A,
  DMAMUX_DMAREQ_ID_TMR20_TRIG = 0x5D,
  DMAMUX_DMAREQ_ID_TMR20_HALL = 0x5E,
  DMAMUX_DMAREQ_ID_DVP = 0x69
} dmamux_requst_id_sel_type;




typedef enum
{
  DMAMUX_SYNC_ID_EXINT0 = 0x00,
  DMAMUX_SYNC_ID_EXINT1 = 0x01,
  DMAMUX_SYNC_ID_EXINT2 = 0x02,
  DMAMUX_SYNC_ID_EXINT3 = 0x03,
  DMAMUX_SYNC_ID_EXINT4 = 0x04,
  DMAMUX_SYNC_ID_EXINT5 = 0x05,
  DMAMUX_SYNC_ID_EXINT6 = 0x06,
  DMAMUX_SYNC_ID_EXINT7 = 0x07,
  DMAMUX_SYNC_ID_EXINT8 = 0x08,
  DMAMUX_SYNC_ID_EXINT9 = 0x09,
  DMAMUX_SYNC_ID_EXINT10 = 0x0A,
  DMAMUX_SYNC_ID_EXINT11 = 0x0B,
  DMAMUX_SYNC_ID_EXINT12 = 0x0C,
  DMAMUX_SYNC_ID_EXINT13 = 0x0D,
  DMAMUX_SYNC_ID_EXINT14 = 0x0E,
  DMAMUX_SYNC_ID_EXINT15 = 0x0F,
  DMAMUX_SYNC_ID_DMAMUX_CH1_EVT = 0x10,
  DMAMUX_SYNC_ID_DMAMUX_CH2_EVT = 0x11,
  DMAMUX_SYNC_ID_DMAMUX_CH3_EVT = 0x12,
  DMAMUX_SYNC_ID_DMAMUX_CH4_EVT = 0x13,
  DMAMUX_SYNC_ID_DMAMUX_CH5_EVT = 0x14,
  DMAMUX_SYNC_ID_DMAMUX_CH6_EVT = 0x15,
  DMAMUX_SYNC_ID_DMAMUX_CH7_EVT = 0x16
} dmamux_sync_id_sel_type;




typedef enum
{
  DMAMUX_SYNC_POLARITY_DISABLE = 0x00,
  DMAMUX_SYNC_POLARITY_RISING = 0x01,
  DMAMUX_SYNC_POLARITY_FALLING = 0x02,
  DMAMUX_SYNC_POLARITY_RISING_FALLING = 0x03
} dmamux_sync_pol_type;




typedef enum
{
  DMAMUX_GEN_ID_EXINT0 = 0x00,
  DMAMUX_GEN_ID_EXINT1 = 0x01,
  DMAMUX_GEN_ID_EXINT2 = 0x02,
  DMAMUX_GEN_ID_EXINT3 = 0x03,
  DMAMUX_GEN_ID_EXINT4 = 0x04,
  DMAMUX_GEN_ID_EXINT5 = 0x05,
  DMAMUX_GEN_ID_EXINT6 = 0x06,
  DMAMUX_GEN_ID_EXINT7 = 0x07,
  DMAMUX_GEN_ID_EXINT8 = 0x08,
  DMAMUX_GEN_ID_EXINT9 = 0x09,
  DMAMUX_GEN_ID_EXINT10 = 0x0A,
  DMAMUX_GEN_ID_EXINT11 = 0x0B,
  DMAMUX_GEN_ID_EXINT12 = 0x0C,
  DMAMUX_GEN_ID_EXINT13 = 0x0D,
  DMAMUX_GEN_ID_EXINT14 = 0x0E,
  DMAMUX_GEN_ID_EXINT15 = 0x0F,
  DMAMUX_GEN_ID_DMAMUX_CH1_EVT = 0x10,
  DMAMUX_GEN_ID_DMAMUX_CH2_EVT = 0x11,
  DMAMUX_GEN_ID_DMAMUX_CH3_EVT = 0x12,
  DMAMUX_GEN_ID_DMAMUX_CH4_EVT = 0x13,
  DMAMUX_GEN_ID_DMAMUX_CH5_EVT = 0x14,
  DMAMUX_GEN_ID_DMAMUX_CH6_EVT = 0x15,
  DMAMUX_GEN_ID_DMAMUX_CH7_EVT = 0x16
} dmamux_gen_id_sel_type;




typedef enum
{
  DMAMUX_GEN_POLARITY_DISABLE = 0x00,
  DMAMUX_GEN_POLARITY_RISING = 0x01,
  DMAMUX_GEN_POLARITY_FALLING = 0x02,
  DMAMUX_GEN_POLARITY_RISING_FALLING = 0x03
} dmamux_gen_pol_type;




typedef struct
{
  uint32_t peripheral_base_addr;
  uint32_t memory_base_addr;
  dma_dir_type direction;
  uint16_t buffer_size;
  confirm_state peripheral_inc_enable;
  confirm_state memory_inc_enable;
  dma_peripheral_data_size_type peripheral_data_width;
  dma_memory_data_size_type memory_data_width;
  confirm_state loop_mode_enable;
  dma_priority_level_type priority;
} dma_init_type;




typedef struct
{
  dmamux_sync_id_sel_type sync_signal_sel;
  uint32_t sync_polarity;
  uint32_t sync_request_number;
  confirm_state sync_event_enable;
  confirm_state sync_enable;
} dmamux_sync_init_type;




typedef struct
{
  dmamux_gen_id_sel_type gen_signal_sel;
  dmamux_gen_pol_type gen_polarity;
  uint32_t gen_request_number;
  confirm_state gen_enable;
} dmamux_gen_init_type;




typedef struct
{



  union
  {
    volatile uint32_t sts;
    struct
    {
      volatile uint32_t gf1 : 1;
      volatile uint32_t fdtf1 : 1;
      volatile uint32_t hdtf1 : 1;
      volatile uint32_t dterrf1 : 1;
      volatile uint32_t gf2 : 1;
      volatile uint32_t fdtf2 : 1;
      volatile uint32_t hdtf2 : 1;
      volatile uint32_t dterrf2 : 1;
      volatile uint32_t gf3 : 1;
      volatile uint32_t fdtf3 : 1;
      volatile uint32_t hdtf3 : 1;
      volatile uint32_t dterrf3 : 1;
      volatile uint32_t gf4 : 1;
      volatile uint32_t fdtf4 : 1;
      volatile uint32_t hdtf4 : 1;
      volatile uint32_t dterrf4 : 1;
      volatile uint32_t gf5 : 1;
      volatile uint32_t fdtf5 : 1;
      volatile uint32_t hdtf5 : 1;
      volatile uint32_t dterrf5 : 1;
      volatile uint32_t gf6 : 1;
      volatile uint32_t fdtf6 : 1;
      volatile uint32_t hdtf6 : 1;
      volatile uint32_t dterrf6 : 1;
      volatile uint32_t gf7 : 1;
      volatile uint32_t fdtf7 : 1;
      volatile uint32_t hdtf7 : 1;
      volatile uint32_t dterrf7 : 1;
      volatile uint32_t reserved1 : 4;
    } sts_bit;
  };




  union
  {
    volatile uint32_t clr;
    struct
    {
      volatile uint32_t gfc1 : 1;
      volatile uint32_t fdtfc1 : 1;
      volatile uint32_t hdtfc1 : 1;
      volatile uint32_t dterrfc1 : 1;
      volatile uint32_t gfc2 : 1;
      volatile uint32_t fdtfc2 : 1;
      volatile uint32_t hdtfc2 : 1;
      volatile uint32_t dterrfc2 : 1;
      volatile uint32_t gfc3 : 1;
      volatile uint32_t fdtfc3 : 1;
      volatile uint32_t hdtfc3 : 1;
      volatile uint32_t dterrfc3 : 1;
      volatile uint32_t gfc4 : 1;
      volatile uint32_t fdtfc4 : 1;
      volatile uint32_t hdtfc4 : 1;
      volatile uint32_t dterrfc4 : 1;
      volatile uint32_t gfc5 : 1;
      volatile uint32_t fdtfc5 : 1;
      volatile uint32_t hdtfc5 : 1;
      volatile uint32_t dterrfc5 : 1;
      volatile uint32_t gfc6 : 1;
      volatile uint32_t fdtfc6 : 1;
      volatile uint32_t hdtfc6 : 1;
      volatile uint32_t dterrfc6 : 1;
      volatile uint32_t gfc7 : 1;
      volatile uint32_t fdtfc7 : 1;
      volatile uint32_t hdtfc7 : 1;
      volatile uint32_t dterrfc7 : 1;
      volatile uint32_t reserved1 : 4;
    } clr_bit;
  };




  volatile uint32_t reserved1[62];




  union
  {
    volatile uint32_t muxsel;
    struct
    {
      volatile uint32_t tblsel : 1;
      volatile uint32_t reserved1 : 31;
    }muxsel_bit;
  };




  volatile uint32_t reserved2[11];




  union
  {
    volatile uint32_t muxsyncsts;
    struct
    {
      volatile uint32_t syncovf : 7;
      volatile uint32_t reserved1 : 25;
    }muxsyncsts_bit;
  };




  union
  {
    volatile uint32_t muxsyncclr;
    struct
    {
      volatile uint32_t syncovfc : 7;
      volatile uint32_t reserved1 : 25;
    }muxsyncclr_bit;
  };




  union
  {
    volatile uint32_t muxgsts;
    struct
    {
      volatile uint32_t trgovf : 4;
      volatile uint32_t reserved1 : 28;
    }muxgsts_bit;
  };



  union
  {
    volatile uint32_t muxgclr;
    struct
    {
      volatile uint32_t trgovfc : 4;
      volatile uint32_t reserved1 : 28;
    }muxgclr_bit;
  };
} dma_type;




typedef struct
{



  union
  {
    volatile uint32_t ctrl;
    struct
    {
      volatile uint32_t chen : 1;
      volatile uint32_t fdtien : 1;
      volatile uint32_t hdtien : 1;
      volatile uint32_t dterrien : 1;
      volatile uint32_t dtd : 1;
      volatile uint32_t lm : 1;
      volatile uint32_t pincm : 1;
      volatile uint32_t mincm : 1;
      volatile uint32_t pwidth : 2;
      volatile uint32_t mwidth : 2;
      volatile uint32_t chpl : 2;
      volatile uint32_t m2m : 1;
      volatile uint32_t reserved1 : 17;
    } ctrl_bit;
  };




  union
  {
    volatile uint32_t dtcnt;
    struct
    {
      volatile uint32_t cnt : 16;
      volatile uint32_t reserved1 : 16;
    } dtcnt_bit;
  };




  union
  {
    volatile uint32_t paddr;
    struct
    {
      volatile uint32_t paddr : 32;
    } paddr_bit;
  };




  union
  {
    volatile uint32_t maddr;
    struct
    {
      volatile uint32_t maddr : 32;
    } maddr_bit;
  };
} dma_channel_type;




typedef struct
{



  union
  {
    volatile uint32_t muxctrl;
    struct
    {
      volatile uint32_t reqsel : 7;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t syncovien : 1;
      volatile uint32_t evtgen : 1;
      volatile uint32_t reserved2 : 6;
      volatile uint32_t syncen : 1;
      volatile uint32_t syncpol : 2;
      volatile uint32_t reqcnt : 5;
      volatile uint32_t syncsel : 5;
      volatile uint32_t reserved3 : 3;
    }muxctrl_bit;
  };
} dmamux_channel_type;




typedef struct
{



  union
  {
    volatile uint32_t gctrl;
    struct
    {
      volatile uint32_t sigsel : 5;
      volatile uint32_t reserved1 : 3;
      volatile uint32_t trgovien : 1;
      volatile uint32_t reserved2 : 7;
      volatile uint32_t gen : 1;
      volatile uint32_t gpol : 2;
      volatile uint32_t greqcnt : 5;
      volatile uint32_t reserved3 : 8;
    }gctrl_bit;
  };
} dmamux_generator_type;
# 744 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_dma.h"
void dma_reset(dma_channel_type *dmax_channely);
void dma_data_number_set(dma_channel_type *dmax_channely, uint16_t data_number);
uint16_t dma_data_number_get(dma_channel_type *dmax_channely);
void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, confirm_state new_state);
void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state);
flag_status dma_flag_get(uint32_t dmax_flag);
void dma_flag_clear(uint32_t dmax_flag);
void dma_default_para_init(dma_init_type *dma_init_struct);
void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct);


void dma_flexible_config(dma_type* dma_x, dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel);
void dmamux_enable(dma_type *dma_x, confirm_state new_state);
void dmamux_init(dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel);
void dmamux_sync_default_para_init(dmamux_sync_init_type *dmamux_sync_init_struct);
void dmamux_sync_config(dmamux_channel_type *dmamux_channelx, dmamux_sync_init_type *dmamux_sync_init_struct);
void dmamux_generator_default_para_init(dmamux_gen_init_type *dmamux_gen_init_struct);
void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_init_type *dmamux_gen_init_struct);
void dmamux_sync_interrupt_enable(dmamux_channel_type *dmamux_channelx, confirm_state new_state);
void dmamux_generator_interrupt_enable(dmamux_generator_type *dmamux_gen_x, confirm_state new_state);
flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag);
void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag);
flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag);
void dmamux_generator_flag_clear(dma_type *dma_x, uint32_t flag);
# 118 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_debug.h" 1
# 95 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_debug.h"
typedef struct
{



  union
  {
    volatile uint32_t pid;
    struct
    {
      volatile uint32_t pid : 32;
    } idcode_bit;
  };




  union
  {
    volatile uint32_t ctrl;
    struct
    {
      volatile uint32_t sleep_debug : 1;
      volatile uint32_t deepsleep_debug : 1;
      volatile uint32_t standby_debug : 1;
      volatile uint32_t reserved1 : 29;
    } ctrl_bit;
  };



  union
  {
    volatile uint32_t apb1_frz;
    struct
    {
      volatile uint32_t tmr2_pause : 1;
      volatile uint32_t tmr3_pause : 1;
      volatile uint32_t tmr4_pause : 1;
      volatile uint32_t tmr5_pause : 1;
      volatile uint32_t tmr6_pause : 1;
      volatile uint32_t tmr7_pause : 1;
      volatile uint32_t tmr12_pause : 1;
      volatile uint32_t tmr13_pause : 1;
      volatile uint32_t tmr14_pause : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t ertc_pause : 1;
      volatile uint32_t wwdt_pause : 1;
      volatile uint32_t wdt_pause : 1;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t ertc_512_pause : 1;
      volatile uint32_t reserved3 : 8;
      volatile uint32_t i2c1_smbus_timeout : 1;
      volatile uint32_t can1_pause : 1;
      volatile uint32_t can2_pause : 1;
      volatile uint32_t i2c2_smbus_timeout : 1;
      volatile uint32_t i2c3_smbus_timeout : 1;
      volatile uint32_t reserved4 : 3;
    } apb1_frz_bit;
  };



  union
  {
    volatile uint32_t apb2_frz;
    struct
    {
      volatile uint32_t tmr1_pause : 1;
      volatile uint32_t tmr8_pause : 1;
      volatile uint32_t reserved1 : 4;
      volatile uint32_t tmr20_pause : 1;
      volatile uint32_t reserved2 : 9;
      volatile uint32_t tmr9_pause : 1;
      volatile uint32_t tmr10_pause : 1;
      volatile uint32_t tmr11_pause : 1;
      volatile uint32_t reserved3 : 13;
    } apb2_frz_bit;
  };

} debug_type;
# 187 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_debug.h"
uint32_t debug_device_id_get(void);
void debug_low_power_mode_set(uint32_t low_power_mode, confirm_state new_state);
void debug_apb1_periph_mode_set(uint32_t apb1_periph, confirm_state new_state);
void debug_apb2_periph_mode_set(uint32_t apb2_periph, confirm_state new_state);
# 121 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_flash.h" 1
# 174 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_flash.h"
typedef enum
{
  FLASH_EOPB0_SRAM_512K = 0x00,
  FLASH_EOPB0_SRAM_448K = 0x01,
  FLASH_EOPB0_SRAM_384K = 0x02,
  FLASH_EOPB0_SRAM_320K = 0x03,
  FLASH_EOPB0_SRAM_256K = 0x04,
  FLASH_EOPB0_SRAM_192K = 0x05,
  FLASH_EOPB0_SRAM_128K = 0x06
} flash_usd_eopb0_type;




typedef enum
{
  FLASH_CLOCK_DIV_2 = 0x00,
  FLASH_CLOCK_DIV_3 = 0x01,
  FLASH_CLOCK_DIV_4 = 0x02
} flash_clock_divider_type;




typedef enum
{
  FLASH_OPERATE_BUSY = 0x00,
  FLASH_PROGRAM_ERROR = 0x01,
  FLASH_EPP_ERROR = 0x02,
  FLASH_OPERATE_DONE = 0x03,
  FLASH_OPERATE_TIMEOUT = 0x04
} flash_status_type;




typedef struct
{



  union
  {
    volatile uint32_t psr;
    struct
    {
      volatile uint32_t reserved1 : 12;
      volatile uint32_t nzw_bst : 1;
      volatile uint32_t nzw_bst_sts : 1;
      volatile uint32_t reserved2 : 18;
    } psr_bit;
  };




  union
  {
    volatile uint32_t unlock;
    struct
    {
      volatile uint32_t ukval : 32;
    } unlock_bit;
  };




  union
  {
    volatile uint32_t usd_unlock;
    struct
    {
      volatile uint32_t usd_ukval : 32;
    } usd_unlock_bit;
  };




  union
  {
    volatile uint32_t sts;
    struct
    {
      volatile uint32_t obf : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t prgmerr : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t epperr : 1;
      volatile uint32_t odf : 1;
      volatile uint32_t reserved3 : 26;
    } sts_bit;
  };




  union
  {
    volatile uint32_t ctrl;
    struct
    {
      volatile uint32_t fprgm : 1;
      volatile uint32_t secers : 1;
      volatile uint32_t bankers : 1;
      volatile uint32_t blkers : 1;
      volatile uint32_t usdprgm : 1;
      volatile uint32_t usders : 1;
      volatile uint32_t erstr : 1;
      volatile uint32_t oplk : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t usdulks : 1;
      volatile uint32_t errie : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t odfie : 1;
      volatile uint32_t reserved3 : 19;
    } ctrl_bit;
  };




  union
  {
    volatile uint32_t addr;
    struct
    {
      volatile uint32_t fa : 32;
    } addr_bit;
  };




  volatile uint32_t reserved1;




  union
  {
    volatile uint32_t usd;
    struct
    {
      volatile uint32_t usderr : 1;
      volatile uint32_t fap : 1;
      volatile uint32_t wdt_ato_en : 1;
      volatile uint32_t depslp_rst : 1;
      volatile uint32_t stdby_rst : 1;
      volatile uint32_t btopt : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t wdt_depslp : 1;
      volatile uint32_t wdt_stdby : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t user_d0 : 8;
      volatile uint32_t user_d1 : 8;
      volatile uint32_t reserved3 : 6;
    } usd_bit;
  };




  union
  {
    volatile uint32_t epps0;
    struct
    {
      volatile uint32_t epps : 32;
    } epps0_bit;
  };




  volatile uint32_t reserved2[2];




  union
  {
    volatile uint32_t epps1;
    struct
    {
      volatile uint32_t epps : 32;
    } epps1_bit;
  };




  volatile uint32_t reserved3[5];




  union
  {
    volatile uint32_t unlock2;
    struct
    {
      volatile uint32_t ukval : 32;
    } unlock2_bit;
  };




  volatile uint32_t reserved4;




  union
  {
    volatile uint32_t sts2;
    struct
    {
      volatile uint32_t obf : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t prgmerr : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t epperr : 1;
      volatile uint32_t odf : 1;
      volatile uint32_t reserved3 : 26;
    } sts2_bit;
  };




  union
  {
    volatile uint32_t ctrl2;
    struct
    {
      volatile uint32_t fprgm : 1;
      volatile uint32_t secers : 1;
      volatile uint32_t bankers : 1;
      volatile uint32_t blkers : 1;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t erstr : 1;
      volatile uint32_t oplk : 1;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t errie : 1;
      volatile uint32_t reserved3 : 1;
      volatile uint32_t odfie : 1;
      volatile uint32_t reserved4 : 19;
    } ctrl2_bit;
  };




  union
  {
    volatile uint32_t addr2;
    struct
    {
      volatile uint32_t fa : 32;
    } addr2_bit;
  };




  union
  {
    volatile uint32_t contr;
    struct
    {
      volatile uint32_t reserved1 : 31;
      volatile uint32_t fcontr_en : 1;
    } contr_bit;
  };




  volatile uint32_t reserved5;




  union
  {
    volatile uint32_t divr;
    struct
    {
      volatile uint32_t fdiv : 2;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t fdiv_sts : 2;
      volatile uint32_t reserved2 : 26;
    } divr_bit;
  };




  volatile uint32_t reserved6[25];




  union
  {
    volatile uint32_t slib_sts2;
    struct
    {
      volatile uint32_t slib_inst_ss : 16;
      volatile uint32_t reserved1 : 16;
    } slib_sts2_bit;
  };




  union
  {
    volatile uint32_t slib_sts0;
    struct
    {
      volatile uint32_t reserved1 : 3;
      volatile uint32_t slib_enf : 1;
      volatile uint32_t reserved2 : 28;
    } slib_sts0_bit;
  };




  union
  {
    volatile uint32_t slib_sts1;
    struct
    {
      volatile uint32_t slib_ss : 16;
      volatile uint32_t slib_es : 16;
    } slib_sts1_bit;
  };




  union
  {
    volatile uint32_t slib_pwd_clr;
    struct
    {
      volatile uint32_t slib_pclr_val : 32;
    } slib_pwd_clr_bit;
  };




  union
  {
    volatile uint32_t slib_misc_sts;
    struct
    {
      volatile uint32_t slib_pwd_err : 1;
      volatile uint32_t slib_pwd_ok : 1;
      volatile uint32_t slib_ulkf : 1;
      volatile uint32_t reserved1 : 13;
      volatile uint32_t slib_rcnt : 9;
      volatile uint32_t reserved2 : 7;
    } slib_misc_sts_bit;
  };




  union
  {
    volatile uint32_t slib_set_pwd;
    struct
    {
      volatile uint32_t slib_pset_val : 32;
    } slib_set_pwd_bit;
  };




  union
  {
    volatile uint32_t slib_set_range0;
    struct
    {
      volatile uint32_t slib_ss_set : 16;
      volatile uint32_t slib_es_set : 16;
    } slib_set_range0_bit;
  };




  union
  {
    volatile uint32_t slib_set_range1;
    struct
    {
      volatile uint32_t slib_iss_set : 16;
      volatile uint32_t reserved1 : 15;
      volatile uint32_t set_slib_strt : 1;
    } slib_set_range1_bit;
  };




  volatile uint32_t reserved7[2];




  union
  {
    volatile uint32_t slib_unlock;
    struct
    {
      volatile uint32_t slib_ukval : 32;
    } slib_unlock_bit;
  };




  union
  {
    volatile uint32_t crc_ctrl;
    struct
    {
      volatile uint32_t crc_ss : 12;
      volatile uint32_t crc_sn : 12;
      volatile uint32_t reserved1 : 7;
      volatile uint32_t crc_strt : 1;
    } crc_ctrl_bit;
  };




  union
  {
    volatile uint32_t crc_chkr;
    struct
    {
      volatile uint32_t crc_chkr : 32;
    } crc_chkr_bit;
  };

} flash_type;




typedef struct
{
  volatile uint16_t fap;
  volatile uint16_t ssb;
  volatile uint16_t data0;
  volatile uint16_t data1;
  volatile uint16_t epp0;
  volatile uint16_t epp1;
  volatile uint16_t epp2;
  volatile uint16_t epp3;
  volatile uint16_t eopb0;
  volatile uint16_t reserved1;
  volatile uint16_t epp4;
  volatile uint16_t epp5;
  volatile uint16_t epp6;
  volatile uint16_t epp7;
  volatile uint16_t reserved2[12];
  volatile uint16_t qspikey[8];
} usd_type;
# 665 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_flash.h"
flag_status flash_flag_get(uint32_t flash_flag);
void flash_flag_clear(uint32_t flash_flag);
flash_status_type flash_operation_status_get(void);
flash_status_type flash_bank1_operation_status_get(void);
flash_status_type flash_bank2_operation_status_get(void);
flash_status_type flash_operation_wait_for(uint32_t time_out);
flash_status_type flash_bank1_operation_wait_for(uint32_t time_out);
flash_status_type flash_bank2_operation_wait_for(uint32_t time_out);
void flash_unlock(void);
void flash_bank1_unlock(void);
void flash_bank2_unlock(void);
void flash_lock(void);
void flash_bank1_lock(void);
void flash_bank2_lock(void);
flash_status_type flash_sector_erase(uint32_t sector_address);
flash_status_type flash_block_erase(uint32_t block_address);
flash_status_type flash_internal_all_erase(void);
flash_status_type flash_bank1_erase(void);
flash_status_type flash_bank2_erase(void);
flash_status_type flash_user_system_data_erase(void);
flash_status_type flash_eopb0_config(flash_usd_eopb0_type data);
flash_status_type flash_word_program(uint32_t address, uint32_t data);
flash_status_type flash_halfword_program(uint32_t address, uint16_t data);
flash_status_type flash_byte_program(uint32_t address, uint8_t data);
flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data);
flash_status_type flash_epp_set(uint32_t *sector_bits);
void flash_epp_status_get(uint32_t *sector_bits);
flash_status_type flash_fap_enable(confirm_state new_state);
flag_status flash_fap_status_get(void);
flash_status_type flash_ssb_set(uint8_t usd_ssb);
uint8_t flash_ssb_status_get(void);
void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state);
flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t inst_start_sector, uint16_t end_sector);
error_status flash_slib_disable(uint32_t pwd);
uint32_t flash_slib_remaining_count_get(void);
flag_status flash_slib_state_get(void);
uint16_t flash_slib_start_sector_get(void);
uint16_t flash_slib_inststart_sector_get(void);
uint16_t flash_slib_end_sector_get(void);
uint32_t flash_crc_calibrate(uint32_t start_sector, uint32_t sector_cnt);
void flash_nzw_boost_enable(confirm_state new_state);
void flash_continue_read_enable(confirm_state new_state);
# 124 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_crc.h" 1
# 54 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_crc.h"
typedef enum
{
  CRC_REVERSE_INPUT_NO_AFFECTE = 0x00,
  CRC_REVERSE_INPUT_BY_BYTE = 0x01,
  CRC_REVERSE_INPUT_BY_HALFWORD = 0x02,
  CRC_REVERSE_INPUT_BY_WORD = 0x03
} crc_reverse_input_type;




typedef enum
{
  CRC_REVERSE_OUTPUT_NO_AFFECTE = 0x00,
  CRC_REVERSE_OUTPUT_DATA = 0x01
} crc_reverse_output_type;




typedef struct
{



  union
  {
    volatile uint32_t dt;
    struct
    {
      volatile uint32_t dt : 32;
    } dt_bit;
  };




  union
  {
    volatile uint32_t cdt;
    struct
    {
      volatile uint32_t cdt : 8 ;
      volatile uint32_t reserved1 : 24 ;
    } cdt_bit;
  };




  union
  {
    volatile uint32_t ctrl;
    struct
    {
      volatile uint32_t rst : 1 ;
      volatile uint32_t reserved1 : 4 ;
      volatile uint32_t revid : 2 ;
      volatile uint32_t revod : 1 ;
      volatile uint32_t reserved2 : 24 ;
    } ctrl_bit;
  };




  volatile uint32_t reserved1;




  union
  {
    volatile uint32_t idt;
    struct
    {
      volatile uint32_t idt : 32;
    } idt_bit;
  };

} crc_type;
# 146 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_crc.h"
void crc_data_reset(void);
uint32_t crc_one_word_calculate(uint32_t data);
uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length);
uint32_t crc_data_get(void);
void crc_common_data_set(uint8_t cdt_value);
uint8_t crc_common_data_get(void);
void crc_init_data_set(uint32_t value);
void crc_reverse_input_data_set(crc_reverse_input_type value);
void crc_reverse_output_data_set(crc_reverse_output_type value);
# 127 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_wwdt.h" 1
# 65 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_wwdt.h"
typedef enum
{
  WWDT_PCLK1_DIV_4096 = 0x00,
  WWDT_PCLK1_DIV_8192 = 0x01,
  WWDT_PCLK1_DIV_16384 = 0x02,
  WWDT_PCLK1_DIV_32768 = 0x03
} wwdt_division_type;




typedef struct
{




  union
  {
    volatile uint32_t ctrl;
    struct
    {
      volatile uint32_t cnt : 7;
      volatile uint32_t wwdten : 1;
      volatile uint32_t reserved1 : 24;
    } ctrl_bit;
  };




  union
  {
    volatile uint32_t cfg;
    struct
    {
      volatile uint32_t win : 7;
      volatile uint32_t div : 2;
      volatile uint32_t rldien : 1;
      volatile uint32_t reserved1 : 22;
    } cfg_bit;
  };




  union
  {
    volatile uint32_t sts;
    struct
    {
      volatile uint32_t rldf : 1;
      volatile uint32_t reserved1 : 31;
    } sts_bit;
  };

} wwdt_type;
# 133 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_wwdt.h"
void wwdt_reset(void);
void wwdt_divider_set(wwdt_division_type division);
void wwdt_flag_clear(void);
void wwdt_enable(uint8_t wwdt_cnt);
void wwdt_interrupt_enable(void);
flag_status wwdt_flag_get(void);
void wwdt_counter_set(uint8_t wwdt_cnt);
void wwdt_window_counter_set(uint8_t window_cnt);
# 130 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_wdt.h" 1
# 68 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_wdt.h"
typedef enum
{
  WDT_CLK_DIV_4 = 0x00,
  WDT_CLK_DIV_8 = 0x01,
  WDT_CLK_DIV_16 = 0x02,
  WDT_CLK_DIV_32 = 0x03,
  WDT_CLK_DIV_64 = 0x04,
  WDT_CLK_DIV_128 = 0x05,
  WDT_CLK_DIV_256 = 0x06
} wdt_division_type;




typedef enum
{
  WDT_CMD_LOCK = 0x0000,
  WDT_CMD_UNLOCK = 0x5555,
  WDT_CMD_ENABLE = 0xCCCC,
  WDT_CMD_RELOAD = 0xAAAA
} wdt_cmd_value_type;




typedef struct
{




  union
  {
    volatile uint32_t cmd;
    struct
    {
      volatile uint32_t cmd : 16;
      volatile uint32_t reserved1 : 16;
    } cmd_bit;
  };




  union
  {
    volatile uint32_t div;
    struct
    {
      volatile uint32_t div : 3;
      volatile uint32_t reserved1 : 29;
    } div_bit;
  };




  union
  {
    volatile uint32_t rld;
    struct
    {
      volatile uint32_t rld : 12;
      volatile uint32_t reserved1 : 20;
    } rld_bit;
  };




  union
  {
    volatile uint32_t sts;
    struct
    {
      volatile uint32_t divf : 1;
      volatile uint32_t rldf : 1;
      volatile uint32_t reserved1 : 30;
    } sts_bit;
  };




  union
  {
    volatile uint32_t win;
    struct
    {
      volatile uint32_t win : 12;
      volatile uint32_t reserved1 : 20;
    } win_bit;
  };
} wdt_type;
# 173 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_wdt.h"
void wdt_enable(void);
void wdt_counter_reload(void);
void wdt_reload_value_set(uint16_t reload_value);
void wdt_divider_set(wdt_division_type division);
void wdt_register_write_enable( confirm_state new_state);
flag_status wdt_flag_get(uint16_t wdt_flag);
void wdt_window_counter_set(uint16_t window_cnt);
# 133 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_exint.h" 1
# 87 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_exint.h"
typedef enum
{
  EXINT_LINE_INTERRUPUT = 0x00,
  EXINT_LINE_EVENT = 0x01
} exint_line_mode_type;




typedef enum
{
  EXINT_TRIGGER_RISING_EDGE = 0x00,
  EXINT_TRIGGER_FALLING_EDGE = 0x01,
  EXINT_TRIGGER_BOTH_EDGE = 0x02
} exint_polarity_config_type;




typedef struct
{
  exint_line_mode_type line_mode;
  uint32_t line_select;
  exint_polarity_config_type line_polarity;
  confirm_state line_enable;
} exint_init_type;




typedef struct
{




  union
  {
    volatile uint32_t inten;
    struct
    {
      volatile uint32_t intenx : 23;
      volatile uint32_t reserved1 : 9;
    } inten_bit;
  };




  union
  {
    volatile uint32_t evten;
    struct
    {
      volatile uint32_t evtenx : 23;
      volatile uint32_t reserved1 : 9;
    } evten_bit;
  };




  union
  {
    volatile uint32_t polcfg1;
    struct
    {
      volatile uint32_t rpx : 23;
      volatile uint32_t reserved1 : 9;
    } polcfg1_bit;
  };




  union
  {
    volatile uint32_t polcfg2;
    struct
    {
      volatile uint32_t fpx : 23;
      volatile uint32_t reserved1 : 9;
    } polcfg2_bit;
  };




  union
  {
    volatile uint32_t swtrg;
    struct
    {
      volatile uint32_t swtx : 23;
      volatile uint32_t reserved1 : 9;
    } swtrg_bit;
  };




  union
  {
    volatile uint32_t intsts;
    struct
    {
      volatile uint32_t linex : 23;
      volatile uint32_t reserved1 : 9;
    } intsts_bit;
  };
} exint_type;
# 209 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_exint.h"
void exint_reset(void);
void exint_default_para_init(exint_init_type *exint_struct);
void exint_init(exint_init_type *exint_struct);
void exint_flag_clear(uint32_t exint_line);
flag_status exint_flag_get(uint32_t exint_line);
void exint_software_interrupt_event_generate(uint32_t exint_line);
void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state);
void exint_event_enable(uint32_t exint_line, confirm_state new_state);
# 136 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_sdio.h" 1
# 120 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_sdio.h"
typedef enum
{
  SDIO_POWER_OFF = 0x00,
  SDIO_POWER_ON = 0x03
} sdio_power_state_type;




typedef enum
{
  SDIO_CLOCK_EDGE_RISING = 0x00,
  SDIO_CLOCK_EDGE_FALLING = 0x01
} sdio_edge_phase_type;




typedef enum
{
  SDIO_BUS_WIDTH_D1 = 0x00,
  SDIO_BUS_WIDTH_D4 = 0x01,
  SDIO_BUS_WIDTH_D8 = 0x02
} sdio_bus_width_type;




typedef enum
{
  SDIO_RESPONSE_NO = 0x00,
  SDIO_RESPONSE_SHORT = 0x01,
  SDIO_RESPONSE_LONG = 0x03
} sdio_reponse_type;




typedef enum
{
  SDIO_WAIT_FOR_NO = 0x00,
  SDIO_WAIT_FOR_INT = 0x01,
  SDIO_WAIT_FOR_PEND = 0x02
} sdio_wait_type;




typedef enum
{
  SDIO_RSP1_INDEX = 0x00,
  SDIO_RSP2_INDEX = 0x01,
  SDIO_RSP3_INDEX = 0x02,
  SDIO_RSP4_INDEX = 0x03
} sdio_rsp_index_type;




typedef enum
{
  SDIO_DATA_BLOCK_SIZE_1B = 0x00,
  SDIO_DATA_BLOCK_SIZE_2B = 0x01,
  SDIO_DATA_BLOCK_SIZE_4B = 0x02,
  SDIO_DATA_BLOCK_SIZE_8B = 0x03,
  SDIO_DATA_BLOCK_SIZE_16B = 0x04,
  SDIO_DATA_BLOCK_SIZE_32B = 0x05,
  SDIO_DATA_BLOCK_SIZE_64B = 0x06,
  SDIO_DATA_BLOCK_SIZE_128B = 0x07,
  SDIO_DATA_BLOCK_SIZE_256B = 0x08,
  SDIO_DATA_BLOCK_SIZE_512B = 0x09,
  SDIO_DATA_BLOCK_SIZE_1024B = 0x0A,
  SDIO_DATA_BLOCK_SIZE_2048B = 0x0B,
  SDIO_DATA_BLOCK_SIZE_4096B = 0x0C,
  SDIO_DATA_BLOCK_SIZE_8192B = 0x0D,
  SDIO_DATA_BLOCK_SIZE_16384B = 0x0E
} sdio_block_size_type;




typedef enum
{
  SDIO_DATA_BLOCK_TRANSFER = 0x00,
  SDIO_DATA_STREAM_TRANSFER = 0x01
} sdio_transfer_mode_type;




typedef enum
{
  SDIO_DATA_TRANSFER_TO_CARD = 0x00,
  SDIO_DATA_TRANSFER_TO_CONTROLLER = 0x01
} sdio_transfer_direction_type;




typedef enum
{
  SDIO_READ_WAIT_CONTROLLED_BY_D2 = 0x00,
  SDIO_READ_WAIT_CONTROLLED_BY_CK = 0x01
} sdio_read_wait_mode_type;




typedef struct
{
  uint32_t argument;
  uint8_t cmd_index;
  sdio_reponse_type rsp_type;
  sdio_wait_type wait_type;
} sdio_command_struct_type;




typedef struct
{
  uint32_t timeout;
  uint32_t data_length;
  sdio_block_size_type block_size;
  sdio_transfer_mode_type transfer_mode;
  sdio_transfer_direction_type transfer_direction;
} sdio_data_struct_type;




typedef struct
{



  union
  {
    volatile uint32_t pwrctrl;
    struct
    {
      volatile uint32_t ps : 2;
      volatile uint32_t reserved1 : 30;
    } pwrctrl_bit;
  };




  union
  {
    volatile uint32_t clkctrl;
    struct
    {
      volatile uint32_t clkdiv_l : 8;
      volatile uint32_t clkoen : 1;
      volatile uint32_t pwrsven : 1;
      volatile uint32_t bypsen : 1;
      volatile uint32_t busws : 2;
      volatile uint32_t clkegs : 1;
      volatile uint32_t hfcen : 1;
      volatile uint32_t clkdiv_h : 2;
      volatile uint32_t reserved1 : 15;
    } clkctrl_bit;
  };




  union
  {
    volatile uint32_t argu;
    struct
    {
      volatile uint32_t argu : 32;
    } argu_bit;
  };




  union
  {
    volatile uint32_t cmdctrl;
    struct
    {
      volatile uint32_t cmdidx : 6;
      volatile uint32_t rspwt : 2;
      volatile uint32_t intwt : 1;
      volatile uint32_t pndwt : 1;
      volatile uint32_t ccsmen : 1;
      volatile uint32_t iosusp : 1;
      volatile uint32_t reserved1 : 20;
    } cmdctrl_bit;
  };




  union
  {
    volatile uint32_t rspcmd;
    struct
    {
      volatile uint32_t rspcmd : 6;
      volatile uint32_t reserved1 : 26;
    } rspcmd_bit;
  };




  union
  {
    volatile uint32_t rsp1;
    struct
    {
      volatile uint32_t cardsts1 : 32;
    } rsp1_bit;
  };




  union
  {
    volatile uint32_t rsp2;
    struct
    {
      volatile uint32_t cardsts2 : 32;
    } rsp2_bit;
  };




  union
  {
    volatile uint32_t rsp3;
    struct
    {
      volatile uint32_t cardsts3 : 32;
    } rsp3_bit;
  };




  union
  {
    volatile uint32_t rsp4;
    struct
    {
      volatile uint32_t cardsts4 : 32;
    } rsp4_bit;
  };




  union
  {
    volatile uint32_t dttmr;
    struct
    {
      volatile uint32_t timeout : 32;
    } dttmr_bit;
  };




  union
  {
    volatile uint32_t dtlen;
    struct
    {
      volatile uint32_t dtlen : 25;
      volatile uint32_t reserved1 : 7;
    } dtlen_bit;
  };




  union
  {
    volatile uint32_t dtctrl;
    struct
    {
      volatile uint32_t tfren : 1;
      volatile uint32_t tfrdir : 1;
      volatile uint32_t tfrmode : 1;
      volatile uint32_t dmaen : 1;
      volatile uint32_t blksize : 4;
      volatile uint32_t rdwtstart : 1;
      volatile uint32_t rdwtstop : 1;
      volatile uint32_t rdwtmode : 1;
      volatile uint32_t ioen : 1;
      volatile uint32_t reserved1 : 20;
    } dtctrl_bit;
  };




  union
  {
    volatile uint32_t dtcnt;
    struct
    {
      volatile uint32_t cnt : 25;
      volatile uint32_t reserved1 : 7;
    } dtcnt_bit;
  };




  union
  {
    volatile uint32_t sts;
    struct
    {
      volatile uint32_t cmdfail : 1;
      volatile uint32_t dtfail : 1;
      volatile uint32_t cmdtimeout : 1;
      volatile uint32_t dttimeout : 1;
      volatile uint32_t txerru : 1;
      volatile uint32_t rxerro : 1;
      volatile uint32_t cmdrspcmpl : 1;
      volatile uint32_t cmdcmpl : 1;
      volatile uint32_t dtcmpl : 1;
      volatile uint32_t sbiterr : 1;
      volatile uint32_t dtblkcmpl : 1;
      volatile uint32_t docmd : 1;
      volatile uint32_t dotx : 1;
      volatile uint32_t dorx : 1;
      volatile uint32_t txbufh : 1;
      volatile uint32_t rxbufh : 1;
      volatile uint32_t txbuff : 1;
      volatile uint32_t rxbuff : 1;
      volatile uint32_t txbufe : 1;
      volatile uint32_t rxbufe : 1;
      volatile uint32_t txbuf : 1;
      volatile uint32_t rxbuf : 1;
      volatile uint32_t ioif : 1;
      volatile uint32_t reserved1 : 9;
    } sts_bit;
  };




  union
  {
    volatile uint32_t intclr;
    struct
    {
      volatile uint32_t cmdfail : 1;
      volatile uint32_t dtfail : 1;
      volatile uint32_t cmdtimeout : 1;
      volatile uint32_t dttimeout : 1;
      volatile uint32_t txerru : 1;
      volatile uint32_t rxerro : 1;
      volatile uint32_t cmdrspcmpl : 1;
      volatile uint32_t cmdcmpl : 1;
      volatile uint32_t dtcmpl : 1;
      volatile uint32_t sbiterr : 1;
      volatile uint32_t dtblkcmpl : 1;
      volatile uint32_t reserved1 : 11;
      volatile uint32_t ioif : 1;
      volatile uint32_t reserved2 : 9;
    } intclr_bit;
  };




  union
  {
    volatile uint32_t inten;
    struct
    {
      volatile uint32_t cmdfailien : 1;
      volatile uint32_t dtfailien : 1;
      volatile uint32_t cmdtimeoutien : 1;
      volatile uint32_t dttimeoutien : 1;
      volatile uint32_t txerruien : 1;
      volatile uint32_t rxerroien : 1;
      volatile uint32_t cmdrspcmplien : 1;
      volatile uint32_t cmdcmplien : 1;
      volatile uint32_t dtcmplien : 1;
      volatile uint32_t sbiterrien : 1;
      volatile uint32_t dtblkcmplien : 1;
      volatile uint32_t docmdien : 1;
      volatile uint32_t dotxien : 1;
      volatile uint32_t dorxien : 1;
      volatile uint32_t txbufhien : 1;
      volatile uint32_t rxbufhien : 1;
      volatile uint32_t txbuffien : 1;
      volatile uint32_t rxbuffien : 1;
      volatile uint32_t txbufeien : 1;
      volatile uint32_t rxbufeien : 1;
      volatile uint32_t txbufien : 1;
      volatile uint32_t rxbufien : 1;
      volatile uint32_t ioifien : 1;
      volatile uint32_t reserved1 : 9;
    } inten_bit;
  };




  volatile uint32_t reserved1[2];




  union
  {
    volatile uint32_t bufcnt;
    struct
    {
      volatile uint32_t cnt : 24;
      volatile uint32_t reserved1 : 8;
    } bufcnt_bit;
  };




  volatile uint32_t reserved2[13];




  union
  {
    volatile uint32_t buf;
    struct
    {
      volatile uint32_t dt : 32;
    } buf_bit;
  };

} sdio_type;
# 579 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_sdio.h"
void sdio_reset(sdio_type *sdio_x);
void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state);
sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x);
void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg);
void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width);
void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state);
void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state);
flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag);
void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag);
void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct);
void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
uint8_t sdio_command_response_get(sdio_type *sdio_x);
uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index);
void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct);
void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
uint32_t sdio_data_counter_get(sdio_type *sdio_x);
uint32_t sdio_data_read(sdio_type *sdio_x);
uint32_t sdio_buffer_counter_get(sdio_type *sdio_x);
void sdio_data_write(sdio_type *sdio_x, uint32_t data);
void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode);
void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state);
void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state);
void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state);
void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state);
# 139 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_xmc.h" 1
# 54 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_xmc.h"
typedef enum
{
  XMC_DATA_ADDR_MUX_DISABLE = 0x00000000,
  XMC_DATA_ADDR_MUX_ENABLE = 0x00000002
} xmc_data_addr_mux_type;




typedef enum
{
  XMC_BURST_MODE_DISABLE = 0x00000000,
  XMC_BURST_MODE_ENABLE = 0x00000100
} xmc_burst_access_mode_type;




typedef enum
{
  XMC_ASYN_WAIT_DISABLE = 0x00000000,
  XMC_ASYN_WAIT_ENABLE = 0x00008000
} xmc_asyn_wait_type;




typedef enum
{
  XMC_WRAPPED_MODE_DISABLE = 0x00000000,
  XMC_WRAPPED_MODE_ENABLE = 0x00000400
} xmc_wrap_mode_type;




typedef enum
{
  XMC_WRITE_OPERATION_DISABLE = 0x00000000,
  XMC_WRITE_OPERATION_ENABLE = 0x00001000
} xmc_write_operation_type;




typedef enum
{
  XMC_WAIT_SIGNAL_DISABLE = 0x00000000,
  XMC_WAIT_SIGNAL_ENABLE = 0x00002000
} xmc_wait_signal_type;




typedef enum
{
  XMC_WRITE_BURST_SYN_DISABLE = 0x00000000,
  XMC_WRITE_BURST_SYN_ENABLE = 0x00080000
} xmc_write_burst_type;




typedef enum
{
  XMC_WRITE_TIMING_DISABLE = 0x00000000,
  XMC_WRITE_TIMING_ENABLE = 0x00004000
} xmc_extended_mode_type;




typedef enum
{
  XMC_WAIT_OPERATION_DISABLE = 0x00000000,
  XMC_WAIT_OPERATION_ENABLE = 0x00000002
} xmc_nand_pccard_wait_type;




typedef enum
{
  XMC_ECC_OPERATION_DISABLE = 0x00000000,
  XMC_ECC_OPERATION_ENABLE = 0x00000040
} xmc_ecc_enable_type;




typedef enum
{
  XMC_BANK1_NOR_SRAM1 = 0x00000000,
  XMC_BANK1_NOR_SRAM2 = 0x00000001,
  XMC_BANK1_NOR_SRAM3 = 0x00000002,
  XMC_BANK1_NOR_SRAM4 = 0x00000003
} xmc_nor_sram_subbank_type;




typedef enum
{
  XMC_BANK2_NAND = 0x00000000,
  XMC_BANK3_NAND = 0x00000001,
  XMC_BANK4_PCCARD = 0x00000002,
  XMC_BANK5_6_SDRAM = 0x00000003
} xmc_class_bank_type;




typedef enum
{
  XMC_DEVICE_SRAM = 0x00000000,
  XMC_DEVICE_PSRAM = 0x00000004,
  XMC_DEVICE_NOR = 0x00000008
} xmc_memory_type;




typedef enum
{
  XMC_BUSTYPE_8_BITS = 0x00000000,
  XMC_BUSTYPE_16_BITS = 0x00000010
} xmc_data_width_type;




typedef enum
{
  XMC_WAIT_SIGNAL_LEVEL_LOW = 0x00000000,
  XMC_WAIT_SIGNAL_LEVEL_HIGH = 0x00000200
} xmc_wait_signal_polarity_type;




typedef enum
{
  XMC_WAIT_SIGNAL_SYN_BEFORE = 0x00000000,
  XMC_WAIT_SIGNAL_SYN_DURING = 0x00000800
} xmc_wait_timing_type;




typedef enum
{
  XMC_ACCESS_MODE_A = 0x00000000,
  XMC_ACCESS_MODE_B = 0x10000000,
  XMC_ACCESS_MODE_C = 0x20000000,
  XMC_ACCESS_MODE_D = 0x30000000
} xmc_access_mode_type;




typedef enum
{
  XMC_ECC_PAGESIZE_256_BYTES = 0x00000000,
  XMC_ECC_PAGESIZE_512_BYTES = 0x00020000,
  XMC_ECC_PAGESIZE_1024_BYTES = 0x00040000,
  XMC_ECC_PAGESIZE_2048_BYTES = 0x00060000,
  XMC_ECC_PAGESIZE_4096_BYTES = 0x00080000,
  XMC_ECC_PAGESIZE_8192_BYTES = 0x000A0000
} xmc_ecc_pagesize_type;




typedef enum
{
  XMC_INT_RISING_EDGE = 0x00000008,
  XMC_INT_LEVEL = 0x00000010,
  XMC_INT_FALLING_EDGE = 0x00000020,
  XMC_INT_ERR = 0x00004000
} xmc_interrupt_sources_type;




typedef enum
{
  XMC_RISINGEDGE_FLAG = 0x00000001,
  XMC_LEVEL_FLAG = 0x00000002,
  XMC_FALLINGEDGE_FLAG = 0x00000004,
  XMC_FEMPT_FLAG = 0x00000040,
  XMC_ERR_FLAG = 0x00000001,
  XMC_BUSY_FLAG = 0x00000020
} xmc_interrupt_flag_type;




typedef enum
{
  XMC_COLUMN_8 = 0x00000000,
  XMC_COLUMN_9 = 0x00000001,
  XMC_COLUMN_10 = 0x00000002,
  XMC_COLUMN_11 = 0x00000003
}xmc_sdram_column_type;




typedef enum
{
  XMC_ROW_11 = 0x00000000,
  XMC_ROW_12 = 0x00000001,
  XMC_ROW_13 = 0x00000002
}xmc_sdram_row_type;




typedef enum
{
  XMC_MEM_WIDTH_8 = 0x00000000,
  XMC_MEM_WIDTH_16 = 0x00000001
}xmc_sdram_width_type;




typedef enum
{
  XMC_INBK_2 = 0x00000000,
  XMC_INBK_4 = 0x00000001
}xmc_sdram_inbk_type;




typedef enum
{
  XMC_CAS_1 = 0x00000001,
  XMC_CAS_2 = 0x00000002,
  XMC_CAS_3 = 0x00000003
}xmc_sdram_cas_type;




typedef enum
{
  XMC_NO_CLK = 0x00000000,
  XMC_CLKDIV_2 = 0x00000002,
  XMC_CLKDIV_3 = 0x00000003,
  XMC_CLKDIV_4 = 0x00000001
}xmc_sdram_clkdiv_type;




typedef enum
{
  XMC_READ_DELAY_0 = 0x00000000,
  XMC_READ_DELAY_1 = 0x00000001,
  XMC_READ_DELAY_2 = 0x00000002,
}xmc_sdram_rd_delay_type;




typedef enum
{
  XMC_SDRAM_BANK1 = 0x00000000,
  XMC_SDRAM_BANK2 = 0x00000001
}xmc_sdram_bank_type;





typedef enum
{
  XMC_DELAY_CYCLE_1 = 0x00000000,
  XMC_DELAY_CYCLE_2 = 0x00000001,
  XMC_DELAY_CYCLE_3 = 0x00000002,
  XMC_DELAY_CYCLE_4 = 0x00000003,
  XMC_DELAY_CYCLE_5 = 0x00000004,
  XMC_DELAY_CYCLE_6 = 0x00000005,
  XMC_DELAY_CYCLE_7 = 0x00000006,
  XMC_DELAY_CYCLE_8 = 0x00000007,
  XMC_DELAY_CYCLE_9 = 0x00000008,
  XMC_DELAY_CYCLE_10 = 0x00000009,
  XMC_DELAY_CYCLE_11 = 0x0000000A,
  XMC_DELAY_CYCLE_12 = 0x0000000B,
  XMC_DELAY_CYCLE_13 = 0x0000000C,
  XMC_DELAY_CYCLE_14 = 0x0000000D,
  XMC_DELAY_CYCLE_15 = 0x0000000E,
  XMC_DELAY_CYCLE_16 = 0x0000000F
}xmc_sdram_delay_type;





typedef enum
{
  XMC_CMD_NORMAL = 0x00000000,
  XMC_CMD_CLK = 0x00000001,
  XMC_CMD_PRECHARG_ALL = 0x00000002,
  XMC_CMD_AUTO_REFRESH = 0x00000003,
  XMC_CMD_LOAD_MODE = 0x00000004,
  XMC_CMD_SELF_REFRESH = 0x00000005,
  XMC_CMD_POWER_DOWN = 0x00000006
}xmc_command_type;




typedef enum
{
  XMC_CMD_BANK1 = 0x00000010,
  XMC_CMD_BANK2 = 0x00000008,
  XMC_CMD_BANK1_2 = 0x00000018
}xmc_cmd_bank1_2_type;





typedef enum
{
  XMC_STATUS_NORMAL = 0x00000000,
  XMC_STATUS_SELF_REFRESH = 0x00000001,
  XMC_STATUS_POWER_DOWN = 0x00000002,
  XMC_STATUS_MASK = 0x00000003
}xmc_bank_status_type;





typedef struct
{
  xmc_nor_sram_subbank_type subbank;
  xmc_extended_mode_type write_timing_enable;
  uint32_t addr_setup_time;
  uint32_t addr_hold_time;
  uint32_t data_setup_time;
  uint32_t bus_latency_time;
  uint32_t clk_psc;
  uint32_t data_latency_time;
  xmc_access_mode_type mode;
} xmc_norsram_timing_init_type;




typedef struct
{
  xmc_nor_sram_subbank_type subbank;
  xmc_data_addr_mux_type data_addr_multiplex;
  xmc_memory_type device;
  xmc_data_width_type bus_type;
  xmc_burst_access_mode_type burst_mode_enable;
  xmc_asyn_wait_type asynwait_enable;
  xmc_wait_signal_polarity_type wait_signal_lv;
  xmc_wrap_mode_type wrapped_mode_enable;
  xmc_wait_timing_type wait_signal_config;
  xmc_write_operation_type write_enable;
  xmc_wait_signal_type wait_signal_enable;
  xmc_extended_mode_type write_timing_enable;
  xmc_write_burst_type write_burst_syn;
} xmc_norsram_init_type;





typedef struct
{
  xmc_class_bank_type class_bank;
  uint32_t mem_setup_time;
  uint32_t mem_waite_time;
  uint32_t mem_hold_time;
  uint32_t mem_hiz_time;
} xmc_nand_pccard_timinginit_type;





typedef struct
{
  xmc_class_bank_type nand_bank;
  xmc_nand_pccard_wait_type wait_enable;
  xmc_data_width_type bus_type;
  xmc_ecc_enable_type ecc_enable;
  xmc_ecc_pagesize_type ecc_pagesize;
  uint32_t delay_time_cycle;
  uint32_t delay_time_ar;
} xmc_nand_init_type;





typedef struct
{
  xmc_nand_pccard_wait_type enable_wait;
  uint32_t delay_time_cr;
  uint32_t delay_time_ar;
} xmc_pccard_init_type;





typedef struct
{
  xmc_sdram_bank_type sdram_bank;
  xmc_sdram_inbk_type internel_banks;
  xmc_sdram_clkdiv_type clkdiv;
  uint8_t write_protection;
  uint8_t burst_read;
  uint8_t read_delay;
  xmc_sdram_column_type column_address;
  xmc_sdram_row_type row_address;
  xmc_sdram_cas_type cas;
  xmc_sdram_width_type width;
} xmc_sdram_init_type;





typedef struct
{
  xmc_sdram_delay_type tmrd;
  xmc_sdram_delay_type txsr;
  xmc_sdram_delay_type tras;
  xmc_sdram_delay_type trc;
  xmc_sdram_delay_type twr;
  xmc_sdram_delay_type trp;
  xmc_sdram_delay_type trcd;
} xmc_sdram_timing_type;





typedef struct
{
  xmc_command_type cmd;
  xmc_cmd_bank1_2_type cmd_banks;
  uint32_t auto_refresh;
  uint32_t data;
} xmc_sdram_cmd_type;

typedef struct
{



  union
  {
    volatile uint32_t bk1ctrl;
    struct
    {
      volatile uint32_t en : 1;
      volatile uint32_t admuxen : 1;
      volatile uint32_t dev : 2;
      volatile uint32_t extmdbw : 2;
      volatile uint32_t noren : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t syncben : 1;
      volatile uint32_t nwpol : 1;
      volatile uint32_t wrapen : 1;
      volatile uint32_t nwtcfg : 1;
      volatile uint32_t wen : 1;
      volatile uint32_t nwsen : 1;
      volatile uint32_t rwtd : 1;
      volatile uint32_t nwasen : 1;
      volatile uint32_t crpgs : 3;
      volatile uint32_t mwmc : 1;
      volatile uint32_t reserved2 : 12;
    } bk1ctrl_bit;
  };




  union
  {
    volatile uint32_t bk1tmg;
    struct
    {
      volatile uint32_t addrst : 4;
      volatile uint32_t addrht : 4;
      volatile uint32_t dtst : 8;
      volatile uint32_t buslat : 4;
      volatile uint32_t clkpsc : 4;
      volatile uint32_t dtlat : 4;
      volatile uint32_t asyncm : 2;
      volatile uint32_t reserved1 : 2;
    } bk1tmg_bit;
  };

} xmc_bank1_ctrl_tmg_reg_type;

typedef struct
{



  union
  {
    volatile uint32_t bk1tmgwr;
    struct
    {
      volatile uint32_t addrst : 4;
      volatile uint32_t addrht : 4;
      volatile uint32_t dtst : 8;
      volatile uint32_t buslat : 4;
      volatile uint32_t reserved1 : 8;
      volatile uint32_t asyncm : 2;
      volatile uint32_t reserved2 : 2;
    } bk1tmgwr_bit;
  };




  volatile uint32_t reserved1;

} xmc_bank1_tmgwr_reg_type;




typedef struct
{



  xmc_bank1_ctrl_tmg_reg_type ctrl_tmg_group[4];




  volatile uint32_t reserved1[57];




  xmc_bank1_tmgwr_reg_type tmgwr_group[4];




  volatile uint32_t reserved2[63];




  union
  {
    volatile uint32_t ext[4];
    struct
    {
      volatile uint32_t buslatw2w : 8;
      volatile uint32_t buslatr2r : 8;
      volatile uint32_t reserved1 : 16;
    } ext_bit[4];
  };

} xmc_bank1_type;




typedef struct
{



  union
  {
    volatile uint32_t bk2ctrl;
    struct
    {
      volatile uint32_t reserved1 : 1;
      volatile uint32_t nwen : 1;
      volatile uint32_t en : 1;
      volatile uint32_t dev : 1;
      volatile uint32_t extmdbw : 2;
      volatile uint32_t eccen : 1;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t tcr : 4;
      volatile uint32_t tar : 4;
      volatile uint32_t eccpgs : 3;
      volatile uint32_t reserved3 : 12;
    } bk2ctrl_bit;
  };




  union
  {
    volatile uint32_t bk2is;
    struct
    {
      volatile uint32_t res : 1;
      volatile uint32_t hls : 1;
      volatile uint32_t fes : 1;
      volatile uint32_t reien : 1;
      volatile uint32_t hlien : 1;
      volatile uint32_t feien : 1;
      volatile uint32_t fifoe : 1;
      volatile uint32_t reserved1 : 25;
    } bk2is_bit;
  };




  union
  {
    volatile uint32_t bk2tmgmem;
    struct
    {
      volatile uint32_t cmst : 8;
      volatile uint32_t cmwt : 8;
      volatile uint32_t cmht : 8;
      volatile uint32_t cmdhizt : 8;
    } bk2tmgmem_bit;
  };




  union
  {
    volatile uint32_t bk2tmgatt;
    struct
    {
      volatile uint32_t amst : 8;
      volatile uint32_t amwt : 8;
      volatile uint32_t amht : 8;
      volatile uint32_t amdhizt : 8;
    } bk2tmgatt_bit;
  };




  volatile uint32_t reserved1;




  union
  {
    volatile uint32_t bk2ecc;
    struct
    {
      volatile uint32_t ecc : 32;
    } bk2ecc_bit;
  };

} xmc_bank2_type;




typedef struct
{



  union
  {
    volatile uint32_t bk3ctrl;
    struct
    {
      volatile uint32_t reserved1 : 1;
      volatile uint32_t nwen : 1;
      volatile uint32_t en : 1;
      volatile uint32_t dev : 1;
      volatile uint32_t extmdbw : 2;
      volatile uint32_t eccen : 1;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t tcr : 4;
      volatile uint32_t tar : 4;
      volatile uint32_t eccpgs : 3;
      volatile uint32_t reserved3 : 12;
    } bk3ctrl_bit;
  };




  union
  {
    volatile uint32_t bk3is;
    struct
    {
      volatile uint32_t res : 1;
      volatile uint32_t hls : 1;
      volatile uint32_t fes : 1;
      volatile uint32_t reien : 1;
      volatile uint32_t hlien : 1;
      volatile uint32_t feien : 1;
      volatile uint32_t fifoe : 1;
      volatile uint32_t reserved1 : 25;
    } bk3is_bit;
  };




  union
  {
    volatile uint32_t bk3tmgmem;
    struct
    {
      volatile uint32_t cmst : 8;
      volatile uint32_t cmwt : 8;
      volatile uint32_t cmht : 8;
      volatile uint32_t cmdhizt : 8;
    } bk3tmgmem_bit;
  };




  union
  {
    volatile uint32_t bk3tmgatt;
    struct
    {
      volatile uint32_t amst : 8;
      volatile uint32_t amwt : 8;
      volatile uint32_t amht : 8;
      volatile uint32_t amdhizt : 8;
    } bk3tmgatt_bit;
  };




  volatile uint32_t reserved1;




  union
  {
    volatile uint32_t bk3ecc;
    struct
    {
      volatile uint32_t ecc : 32;
    } bk3ecc_bit;
  };
} xmc_bank3_type;




typedef struct
{




  union
  {
    volatile uint32_t bk4ctrl;
    struct
    {
      volatile uint32_t reserved1 : 1;
      volatile uint32_t nwen : 1;
      volatile uint32_t en : 1;
      volatile uint32_t dev : 1;
      volatile uint32_t extmdbw : 2;
      volatile uint32_t eccen : 1;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t tcr : 4;
      volatile uint32_t tar : 4;
      volatile uint32_t eccpgs : 3;
      volatile uint32_t reserved3 : 12;
    } bk4ctrl_bit;
  };




  union
  {
    volatile uint32_t bk4is;
    struct
    {
      volatile uint32_t res : 1;
      volatile uint32_t hls : 1;
      volatile uint32_t fes : 1;
      volatile uint32_t reien : 1;
      volatile uint32_t hlien : 1;
      volatile uint32_t feien : 1;
      volatile uint32_t fifoe : 1;
      volatile uint32_t reserved1 : 25;
    } bk4is_bit;
  };




  union
  {
    volatile uint32_t bk4tmgmem;
    struct
    {
      volatile uint32_t cmst : 8;
      volatile uint32_t cmwt : 8;
      volatile uint32_t cmht : 8;
      volatile uint32_t cmdhizt : 8;
    } bk4tmgmem_bit;
  };




  union
  {
    volatile uint32_t bk4tmgatt;
    struct
    {
      volatile uint32_t amst : 8;
      volatile uint32_t amwt : 8;
      volatile uint32_t amht : 8;
      volatile uint32_t amdhizt : 8;
    } bk4tmgatt_bit;
  };




  union
  {
    volatile uint32_t bk4tmgio;
    struct
    {
      volatile uint32_t iost : 8;
      volatile uint32_t iowt : 8;
      volatile uint32_t ioht : 8;
      volatile uint32_t iohizt : 8;
    } bk4tmgio_bit;
  };
} xmc_bank4_type;




typedef struct
{



  union
  {
    volatile uint32_t ctrl[2];
    struct
    {
      volatile uint32_t ca : 2;
      volatile uint32_t ra : 2;
      volatile uint32_t db : 2;
      volatile uint32_t inbk : 1;
      volatile uint32_t cas : 2;
      volatile uint32_t wrp : 1;
      volatile uint32_t clkdiv : 2;
      volatile uint32_t bstr : 1;
      volatile uint32_t rd : 2;
      volatile uint32_t reserved1 : 17;
    } ctrl_bit[2];
  };




  union
  {
    volatile uint32_t tm[2];
    struct
    {
      volatile uint32_t tmrd : 4;
      volatile uint32_t txsr : 4;
      volatile uint32_t tras : 4;
      volatile uint32_t trc : 4;
      volatile uint32_t twr : 4;
      volatile uint32_t trp : 4;
      volatile uint32_t trcd : 4;
      volatile uint32_t reserved1 : 4;
    } tm_bit[2];

  };




  union
  {
    volatile uint32_t cmd;
    struct
    {
      volatile uint32_t cmd : 3;
      volatile uint32_t bk2 : 1;
      volatile uint32_t bk1 : 1;
      volatile uint32_t art : 4;
      volatile uint32_t mrd : 13;
      volatile uint32_t reserved1 : 10;
    } cmd_bit;
  };




  union
  {
    volatile uint32_t rcnt;
    struct
    {
      volatile uint32_t errc : 1;
      volatile uint32_t rc : 13;
      volatile uint32_t erien : 1;
      volatile uint32_t reserved1 : 17;
    } rcnt_bit;
  };




  union
  {
    volatile uint32_t sts;
    struct
    {
      volatile uint32_t err : 1;
      volatile uint32_t bk1sts : 2;
      volatile uint32_t bk2sts : 2;
      volatile uint32_t busy : 1;
      volatile uint32_t reserved1 : 26;
    } sts_bit;
  };
}xmc_sdram_type;
# 1019 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_xmc.h"
void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank);
void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct);
void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
                                xmc_norsram_timing_init_type* xmc_w_timing_struct);
void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct);
void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
                                          xmc_norsram_timing_init_type* xmc_w_timing_struct);
void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state);
void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing);
void xmc_nand_reset(xmc_class_bank_type xmc_bank);
void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct);
void xmc_nand_timing_config(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
                            xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct);
void xmc_nand_default_para_init(xmc_nand_init_type* xmc_nand_init_struct);
void xmc_nand_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
                                       xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct);
void xmc_nand_enable(xmc_class_bank_type xmc_bank, confirm_state new_state);
void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state);
uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank);
void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state);
flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
void xmc_pccard_reset(void);
void xmc_pccard_init(xmc_pccard_init_type* xmc_pccard_init_struct);
void xmc_pccard_timing_config(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
                              xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct,
                              xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct);
void xmc_pccard_default_para_init(xmc_pccard_init_type* xmc_pccard_init_struct);
void xmc_pccard_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
                                         xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct,
                                         xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct);
void xmc_pccard_enable(confirm_state new_state);
void xmc_sdram_reset(xmc_sdram_bank_type xmc_bank);
void xmc_sdram_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct);
void xmc_sdram_default_para_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct);
void xmc_sdram_cmd(xmc_sdram_cmd_type *xmc_sdram_cmd_struct);
uint32_t xmc_sdram_status_get(xmc_sdram_bank_type xmc_bank);
void xmc_sdram_refresh_counter_set(uint32_t counter);
void xmc_sdram_auto_refresh_set(uint32_t number);
# 142 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_acc.h" 1
# 74 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_acc.h"
typedef struct
{




  union
  {
    volatile uint32_t sts;
    struct
    {
      volatile uint32_t calrdy : 1;
      volatile uint32_t rslost : 1;
      volatile uint32_t reserved1 : 30;
    } sts_bit;
  };




  union
  {
    volatile uint32_t ctrl1;
    struct
    {
      volatile uint32_t calon : 1;
      volatile uint32_t entrim : 1;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t eien : 1;
      volatile uint32_t calrdyien : 1;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t step : 4;
      volatile uint32_t reserved3 : 20;
    } ctrl1_bit;
  };




  union
  {
    volatile uint32_t ctrl2;
    struct
    {
      volatile uint32_t hickcal : 8;
      volatile uint32_t hicktrim : 6;
      volatile uint32_t reserved1 : 18;
    } ctrl2_bit;
  };




  union
  {
    volatile uint32_t c1;
    struct
    {
      volatile uint32_t c1 : 16;
      volatile uint32_t reserved1 : 16;
    } c1_bit;
  };




  union
  {
    volatile uint32_t c2;
    struct
    {
      volatile uint32_t c2 : 16;
      volatile uint32_t reserved1 : 16;
    } c2_bit;
  };




  union
  {
    volatile uint32_t c3;
    struct
    {
      volatile uint32_t c3 : 16;
      volatile uint32_t reserved1 : 16;
    } c3_bit;
  };
} acc_type;
# 174 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_acc.h"
void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state);
void acc_step_set(uint8_t step_value);
void acc_sof_select(uint16_t sof_sel);
void acc_interrupt_enable(uint16_t acc_int, confirm_state new_state);
uint8_t acc_hicktrim_get(void);
uint8_t acc_hickcal_get(void);
void acc_write_c1(uint16_t acc_c1_value);
void acc_write_c2(uint16_t acc_c2_value);
void acc_write_c3(uint16_t acc_c3_value);
uint16_t acc_read_c1(void);
uint16_t acc_read_c2(void);
uint16_t acc_read_c3(void);
flag_status acc_flag_get(uint16_t acc_flag);
void acc_flag_clear(uint16_t acc_flag);
# 145 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_misc.h" 1
# 65 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_misc.h"
typedef enum
{
  NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x7),
  NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x6),
  NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x5),
  NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x4),
  NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x3)
} nvic_priority_group_type;




typedef enum
{
  NVIC_LP_SLEEPONEXIT = 0x02,
  NVIC_LP_SLEEPDEEP = 0x04,
  NVIC_LP_SEVONPEND = 0x10
} nvic_lowpower_mode_type;




typedef enum
{
  SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8 = ((uint32_t)0x00000000),
  SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV = ((uint32_t)0x00000004)
} systick_clock_source_type;
# 101 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_misc.h"
void nvic_system_reset(void);
void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority);
void nvic_irq_disable(IRQn_Type irqn);
void nvic_priority_group_config(nvic_priority_group_type priority_group);
void nvic_vector_table_set(uint32_t base, uint32_t offset);
void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state);
void systick_clock_source_config(systick_clock_source_type source);
# 148 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_edma.h" 1
# 148 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_edma.h"
typedef enum
{
  EDMA_MEMORY_0 = 0x00,
  EDMA_MEMORY_1 = 0x01
} edma_memory_type;




typedef enum
{
  EDMA_DIR_PERIPHERAL_TO_MEMORY = 0x00,
  EDMA_DIR_MEMORY_TO_PERIPHERAL = 0x01,
  EDMA_DIR_MEMORY_TO_MEMORY = 0x02
} edma_dir_type;




typedef enum
{
  EDMA_PERIPHERAL_DATA_WIDTH_BYTE = 0x00,
  EDMA_PERIPHERAL_DATA_WIDTH_HALFWORD = 0x01,
  EDMA_PERIPHERAL_DATA_WIDTH_WORD = 0x02
} edma_peripheral_data_size_type;




typedef enum
{
  EDMA_MEMORY_DATA_WIDTH_BYTE = 0x00,
  EDMA_MEMORY_DATA_WIDTH_HALFWORD = 0x01,
  EDMA_MEMORY_DATA_WIDTH_WORD = 0x02
} edma_memory_data_size_type;




typedef enum
{
  EDMA_PRIORITY_LOW = 0x00,
  EDMA_PRIORITY_MEDIUM = 0x01,
  EDMA_PRIORITY_HIGH = 0x02,
  EDMA_PRIORITY_VERY_HIGH = 0x03
} edma_priority_level_type;




typedef enum
{
  EDMA_FIFO_THRESHOLD_1QUARTER = 0x00,
  EDMA_FIFO_THRESHOLD_HALF = 0x01,
  EDMA_FIFO_THRESHOLD_3QUARTER = 0x02,
  EDMA_FIFO_THRESHOLD_FULL = 0x03
} edma_fifo_threshold_type;




typedef enum
{
  EDMA_FIFO_STATUS_LESS_1QUARTER = 0x00,
  EDMA_FIFO_STATUS_1QUARTER = 0x01,
  EDMA_FIFO_STATUS_HALF = 0x02,
  EDMA_FIFO_STATUS_3QUARTER = 0x03,
  EDMA_FIFO_STATUS_EMPTY = 0x04,
  EDMA_FIFO_STATUS_FULL = 0x05
} edma_fifo_stutas_type;




typedef enum
{
  EDMA_MEMORY_SINGLE = 0x00,
  EDMA_MEMORY_BURST_4 = 0x01,
  EDMA_MEMORY_BURST_8 = 0x02,
  EDMA_MEMORY_BURST_16 = 0x03
} edma_memory_burst_type;




typedef enum
{
  EDMA_PERIPHERAL_SINGLE = 0x00,
  EDMA_PERIPHERAL_BURST_4 = 0x01,
  EDMA_PERIPHERAL_BURST_8 = 0x02,
  EDMA_PERIPHERAL_BURST_16 = 0x03
} edma_peripheral_burst_type;




typedef enum
{
  EDMA_PERIPHERAL_INC_PSIZE = 0x00,
  EDMA_PERIPHERAL_INC_4_BYTE = 0x01
} edma_peripheral_inc_offset_type;




typedef enum
{
  EDMAMUX_DMAREQ_ID_REQ_G1 = 0x01,
  EDMAMUX_DMAREQ_ID_REQ_G2 = 0x02,
  EDMAMUX_DMAREQ_ID_REQ_G3 = 0x03,
  EDMAMUX_DMAREQ_ID_REQ_G4 = 0x04,
  EDMAMUX_DMAREQ_ID_ADC1 = 0x05,
  EDMAMUX_DMAREQ_ID_ADC2 = 0x24,
  EDMAMUX_DMAREQ_ID_ADC3 = 0x25,
  EDMAMUX_DMAREQ_ID_DAC1 = 0x06,
  EDMAMUX_DMAREQ_ID_DAC2 = 0x29,
  EDMAMUX_DMAREQ_ID_TMR6_OVERFLOW = 0x08,
  EDMAMUX_DMAREQ_ID_TMR7_OVERFLOW = 0x09,
  EDMAMUX_DMAREQ_ID_SPI1_RX = 0x0A,
  EDMAMUX_DMAREQ_ID_SPI1_TX = 0x0B,
  EDMAMUX_DMAREQ_ID_SPI2_RX = 0x0C,
  EDMAMUX_DMAREQ_ID_SPI2_TX = 0x0D,
  EDMAMUX_DMAREQ_ID_SPI3_RX = 0x0E,
  EDMAMUX_DMAREQ_ID_SPI3_TX = 0x0F,
  EDMAMUX_DMAREQ_ID_SPI4_RX = 0x6A,
  EDMAMUX_DMAREQ_ID_SPI4_TX = 0x6B,
  EDMAMUX_DMAREQ_ID_I2S2_EXT_RX = 0x6E,
  EDMAMUX_DMAREQ_ID_I2S2_EXT_TX = 0x6F,
  EDMAMUX_DMAREQ_ID_I2S3_EXT_RX = 0x70,
  EDMAMUX_DMAREQ_ID_I2S3_EXT_TX = 0x71,
  EDMAMUX_DMAREQ_ID_I2C1_RX = 0x10,
  EDMAMUX_DMAREQ_ID_I2C1_TX = 0x11,
  EDMAMUX_DMAREQ_ID_I2C2_RX = 0x12,
  EDMAMUX_DMAREQ_ID_I2C2_TX = 0x13,
  EDMAMUX_DMAREQ_ID_I2C3_RX = 0x14,
  EDMAMUX_DMAREQ_ID_I2C3_TX = 0x15,
  EDMAMUX_DMAREQ_ID_USART1_RX = 0x18,
  EDMAMUX_DMAREQ_ID_USART1_TX = 0x19,
  EDMAMUX_DMAREQ_ID_USART2_RX = 0x1A,
  EDMAMUX_DMAREQ_ID_USART2_TX = 0x1B,
  EDMAMUX_DMAREQ_ID_USART3_RX = 0x1C,
  EDMAMUX_DMAREQ_ID_USART3_TX = 0x1D,
  EDMAMUX_DMAREQ_ID_UART4_RX = 0x1E,
  EDMAMUX_DMAREQ_ID_UART4_TX = 0x1F,
  EDMAMUX_DMAREQ_ID_UART5_RX = 0x20,
  EDMAMUX_DMAREQ_ID_UART5_TX = 0x21,
  EDMAMUX_DMAREQ_ID_USART6_RX = 0x72,
  EDMAMUX_DMAREQ_ID_USART6_TX = 0x73,
  EDMAMUX_DMAREQ_ID_UART7_RX = 0x74,
  EDMAMUX_DMAREQ_ID_UART7_TX = 0x75,
  EDMAMUX_DMAREQ_ID_UART8_RX = 0x76,
  EDMAMUX_DMAREQ_ID_UART8_TX = 0x77,
  EDMAMUX_DMAREQ_ID_SDIO1 = 0x27,
  EDMAMUX_DMAREQ_ID_SDIO2 = 0x67,
  EDMAMUX_DMAREQ_ID_QSPI1 = 0x28,
  EDMAMUX_DMAREQ_ID_QSPI2 = 0x68,
  EDMAMUX_DMAREQ_ID_TMR1_CH1 = 0x2A,
  EDMAMUX_DMAREQ_ID_TMR1_CH2 = 0x2B,
  EDMAMUX_DMAREQ_ID_TMR1_CH3 = 0x2C,
  EDMAMUX_DMAREQ_ID_TMR1_CH4 = 0x2D,
  EDMAMUX_DMAREQ_ID_TMR1_OVERFLOW = 0x2E,
  EDMAMUX_DMAREQ_ID_TMR1_TRIG = 0x2F,
  EDMAMUX_DMAREQ_ID_TMR1_HALL = 0x30,
  EDMAMUX_DMAREQ_ID_TMR8_CH1 = 0x31,
  EDMAMUX_DMAREQ_ID_TMR8_CH2 = 0x32,
  EDMAMUX_DMAREQ_ID_TMR8_CH3 = 0x33,
  EDMAMUX_DMAREQ_ID_TMR8_CH4 = 0x34,
  EDMAMUX_DMAREQ_ID_TMR8_OVERFLOW = 0x35,
  EDMAMUX_DMAREQ_ID_TMR8_TRIG = 0x36,
  EDMAMUX_DMAREQ_ID_TMR8_HALL = 0x37,
  EDMAMUX_DMAREQ_ID_TMR2_CH1 = 0x38,
  EDMAMUX_DMAREQ_ID_TMR2_CH2 = 0x39,
  EDMAMUX_DMAREQ_ID_TMR2_CH3 = 0x3A,
  EDMAMUX_DMAREQ_ID_TMR2_CH4 = 0x3B,
  EDMAMUX_DMAREQ_ID_TMR2_OVERFLOW = 0x3C,
  EDMAMUX_DMAREQ_ID_TMR2_TRIG = 0x7E,
  EDMAMUX_DMAREQ_ID_TMR3_CH1 = 0x3D,
  EDMAMUX_DMAREQ_ID_TMR3_CH2 = 0x3E,
  EDMAMUX_DMAREQ_ID_TMR3_CH3 = 0x3F,
  EDMAMUX_DMAREQ_ID_TMR3_CH4 = 0x40,
  EDMAMUX_DMAREQ_ID_TMR3_OVERFLOW = 0x41,
  EDMAMUX_DMAREQ_ID_TMR3_TRIG = 0x42,
  EDMAMUX_DMAREQ_ID_TMR4_CH1 = 0x43,
  EDMAMUX_DMAREQ_ID_TMR4_CH2 = 0x44,
  EDMAMUX_DMAREQ_ID_TMR4_CH3 = 0x45,
  EDMAMUX_DMAREQ_ID_TMR4_CH4 = 0x46,
  EDMAMUX_DMAREQ_ID_TMR4_OVERFLOW = 0x47,
  EDMAMUX_DMAREQ_ID_TMR4_TRIG = 0x7F,
  EDMAMUX_DMAREQ_ID_TMR5_CH1 = 0x48,
  EDMAMUX_DMAREQ_ID_TMR5_CH2 = 0x49,
  EDMAMUX_DMAREQ_ID_TMR5_CH3 = 0x4A,
  EDMAMUX_DMAREQ_ID_TMR5_CH4 = 0x4B,
  EDMAMUX_DMAREQ_ID_TMR5_OVERFLOW = 0x4C,
  EDMAMUX_DMAREQ_ID_TMR5_TRIG = 0x4D,
  EDMAMUX_DMAREQ_ID_TMR20_CH1 = 0x56,
  EDMAMUX_DMAREQ_ID_TMR20_CH2 = 0x57,
  EDMAMUX_DMAREQ_ID_TMR20_CH3 = 0x58,
  EDMAMUX_DMAREQ_ID_TMR20_CH4 = 0x59,
  EDMAMUX_DMAREQ_ID_TMR20_OVERFLOW = 0x5A,
  EDMAMUX_DMAREQ_ID_TMR20_TRIG = 0x5D,
  EDMAMUX_DMAREQ_ID_TMR20_HALL = 0x5E,
  EDMAMUX_DMAREQ_ID_DVP = 0x69
} edmamux_requst_id_sel_type;




typedef enum
{
  EDMAMUX_SYNC_ID_EXINT0 = 0x00,
  EDMAMUX_SYNC_ID_EXINT1 = 0x01,
  EDMAMUX_SYNC_ID_EXINT2 = 0x02,
  EDMAMUX_SYNC_ID_EXINT3 = 0x03,
  EDMAMUX_SYNC_ID_EXINT4 = 0x04,
  EDMAMUX_SYNC_ID_EXINT5 = 0x05,
  EDMAMUX_SYNC_ID_EXINT6 = 0x06,
  EDMAMUX_SYNC_ID_EXINT7 = 0x07,
  EDMAMUX_SYNC_ID_EXINT8 = 0x08,
  EDMAMUX_SYNC_ID_EXINT9 = 0x09,
  EDMAMUX_SYNC_ID_EXINT10 = 0x0A,
  EDMAMUX_SYNC_ID_EXINT11 = 0x0B,
  EDMAMUX_SYNC_ID_EXINT12 = 0x0C,
  EDMAMUX_SYNC_ID_EXINT13 = 0x0D,
  EDMAMUX_SYNC_ID_EXINT14 = 0x0E,
  EDMAMUX_SYNC_ID_EXINT15 = 0x0F,
  EDMAMUX_SYNC_ID_DMAMUX_CH1_EVT = 0x10,
  EDMAMUX_SYNC_ID_DMAMUX_CH2_EVT = 0x11,
  EDMAMUX_SYNC_ID_DMAMUX_CH3_EVT = 0x12,
  EDMAMUX_SYNC_ID_DMAMUX_CH4_EVT = 0x13,
  EDMAMUX_SYNC_ID_DMAMUX_CH5_EVT = 0x14,
  EDMAMUX_SYNC_ID_DMAMUX_CH6_EVT = 0x15,
  EDMAMUX_SYNC_ID_DMAMUX_CH7_EVT = 0x16,
  EDMAMUX_SYNC_ID_DMAMUX_CH8_EVT = 0x17
} edmamux_sync_id_sel_type;




typedef enum
{
  EDMAMUX_SYNC_POLARITY_DISABLE = 0x00,
  EDMAMUX_SYNC_POLARITY_RISING = 0x01,
  EDMAMUX_SYNC_POLARITY_FALLING = 0x02,
  EDMAMUX_SYNC_POLARITY_RISING_FALLING = 0x03
} edmamux_sync_pol_type;




typedef enum
{
  EDMAMUX_GEN_ID_EXINT0 = 0x00,
  EDMAMUX_GEN_ID_EXINT1 = 0x01,
  EDMAMUX_GEN_ID_EXINT2 = 0x02,
  EDMAMUX_GEN_ID_EXINT3 = 0x03,
  EDMAMUX_GEN_ID_EXINT4 = 0x04,
  EDMAMUX_GEN_ID_EXINT5 = 0x05,
  EDMAMUX_GEN_ID_EXINT6 = 0x06,
  EDMAMUX_GEN_ID_EXINT7 = 0x07,
  EDMAMUX_GEN_ID_EXINT8 = 0x08,
  EDMAMUX_GEN_ID_EXINT9 = 0x09,
  EDMAMUX_GEN_ID_EXINT10 = 0x0A,
  EDMAMUX_GEN_ID_EXINT11 = 0x0B,
  EDMAMUX_GEN_ID_EXINT12 = 0x0C,
  EDMAMUX_GEN_ID_EXINT13 = 0x0D,
  EDMAMUX_GEN_ID_EXINT14 = 0x0E,
  EDMAMUX_GEN_ID_EXINT15 = 0x0F,
  EDMAMUX_GEN_ID_DMAMUX_CH1_EVT = 0x10,
  EDMAMUX_GEN_ID_DMAMUX_CH2_EVT = 0x11,
  EDMAMUX_GEN_ID_DMAMUX_CH3_EVT = 0x12,
  EDMAMUX_GEN_ID_DMAMUX_CH4_EVT = 0x13,
  EDMAMUX_GEN_ID_DMAMUX_CH5_EVT = 0x14,
  EDMAMUX_GEN_ID_DMAMUX_CH6_EVT = 0x15,
  EDMAMUX_GEN_ID_DMAMUX_CH7_EVT = 0x16,
  EDMAMUX_GEN_ID_DMAMUX_CH8_EVT = 0x17
} edmamux_gen_id_sel_type;




typedef enum
{
  EDMAMUX_GEN_POLARITY_DISABLE = 0x00,
  EDMAMUX_GEN_POLARITY_RISING = 0x01,
  EDMAMUX_GEN_POLARITY_FALLING = 0x02,
  EDMAMUX_GEN_POLARITY_RISING_FALLING = 0x03
} edmamux_gen_pol_type;




typedef struct
{
  uint32_t peripheral_base_addr;
  uint32_t memory0_base_addr;
  edma_dir_type direction;
  uint16_t buffer_size;
  confirm_state peripheral_inc_enable;
  confirm_state memory_inc_enable;
  edma_peripheral_data_size_type peripheral_data_width;
  edma_memory_data_size_type memory_data_width;
  confirm_state loop_mode_enable;
  edma_priority_level_type priority;
  confirm_state fifo_mode_enable;
  edma_fifo_threshold_type fifo_threshold;
  edma_memory_burst_type memory_burst_mode;
  edma_peripheral_burst_type peripheral_burst_mode;
} edma_init_type;




typedef struct
{
  edmamux_sync_id_sel_type sync_signal_sel;
  edmamux_sync_pol_type sync_polarity;
  uint32_t sync_request_number;
  confirm_state sync_event_enable;
  confirm_state sync_enable;
} edmamux_sync_init_type;




typedef struct
{
  edmamux_gen_id_sel_type gen_signal_sel;
  edmamux_gen_pol_type gen_polarity;
  uint32_t gen_request_number;
  confirm_state gen_enable;
} edmamux_gen_init_type;




typedef struct
{



  union
  {
    volatile uint32_t sts1;
    struct
    {
      volatile uint32_t ferrf1 : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t dmerrf1 : 1;
      volatile uint32_t dterrf1 : 1;
      volatile uint32_t hdtf1 : 1;
      volatile uint32_t fdtf1 : 1;
      volatile uint32_t ferrf2 : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t dmerrf2 : 1;
      volatile uint32_t dterrf2 : 1;
      volatile uint32_t hdtf2 : 1;
      volatile uint32_t fdtf2 : 1;
      volatile uint32_t reserved3 : 4;
      volatile uint32_t ferrf3 : 1;
      volatile uint32_t reserved4 : 1;
      volatile uint32_t dmerrf3 : 1;
      volatile uint32_t dterrf3 : 1;
      volatile uint32_t hdtf3 : 1;
      volatile uint32_t fdtf3 : 1;
      volatile uint32_t ferrf4 : 1;
      volatile uint32_t reserved5 : 1;
      volatile uint32_t dmerrf4 : 1;
      volatile uint32_t dterrf4 : 1;
      volatile uint32_t hdtf4 : 1;
      volatile uint32_t fdtf4 : 1;
      volatile uint32_t reserved6 : 4;
    } sts1_bit;
  };



  union
  {
    volatile uint32_t sts2;
    struct
    {
      volatile uint32_t ferrf5 : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t dmerrf5 : 1;
      volatile uint32_t dterrf5 : 1;
      volatile uint32_t hdtf5 : 1;
      volatile uint32_t fdtf5 : 1;
      volatile uint32_t ferrf6 : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t dmerrf6 : 1;
      volatile uint32_t dterrf6 : 1;
      volatile uint32_t hdtf6 : 1;
      volatile uint32_t fdtf6 : 1;
      volatile uint32_t reserved3 : 4;
      volatile uint32_t ferrf7 : 1;
      volatile uint32_t reserved4 : 1;
      volatile uint32_t dmerrf7 : 1;
      volatile uint32_t dterrf7 : 1;
      volatile uint32_t hdtf7 : 1;
      volatile uint32_t fdtf7 : 1;
      volatile uint32_t ferrf8 : 1;
      volatile uint32_t reserved5 : 1;
      volatile uint32_t dmerrf8 : 1;
      volatile uint32_t dterrf8 : 1;
      volatile uint32_t hdtf8 : 1;
      volatile uint32_t fdtf8 : 1;
      volatile uint32_t reserved6 : 4;
    } sts2_bit;
  };



  union
  {
    volatile uint32_t clr1;
    struct
    {
      volatile uint32_t ferrfc1 : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t dmerrfc1 : 1;
      volatile uint32_t dterrfc1 : 1;
      volatile uint32_t hdtfc1 : 1;
      volatile uint32_t fdtfc1 : 1;
      volatile uint32_t ferrfc2 : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t dmerrfc2 : 1;
      volatile uint32_t dterrfc2 : 1;
      volatile uint32_t hdtfc2 : 1;
      volatile uint32_t fdtfc2 : 1;
      volatile uint32_t reserved3 : 4;
      volatile uint32_t ferrfc3 : 1;
      volatile uint32_t reserved4 : 1;
      volatile uint32_t dmerrfc3 : 1;
      volatile uint32_t dterrfc3 : 1;
      volatile uint32_t hdtfc3 : 1;
      volatile uint32_t fdtfc3 : 1;
      volatile uint32_t ferrfc4 : 1;
      volatile uint32_t reserved5 : 1;
      volatile uint32_t dmerrfc4 : 1;
      volatile uint32_t dterrfc4 : 1;
      volatile uint32_t hdtfc4 : 1;
      volatile uint32_t fdtfc4 : 1;
      volatile uint32_t reserved6 : 4;
    } clr1_bit;
  };



  union
  {
    volatile uint32_t clr2;
    struct
    {
      volatile uint32_t ferrfc5 : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t dmerrfc5 : 1;
      volatile uint32_t dterrfc5 : 1;
      volatile uint32_t hdtfc5 : 1;
      volatile uint32_t fdtfc5 : 1;
      volatile uint32_t ferrfc6 : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t dmerrfc6 : 1;
      volatile uint32_t dterrfc6 : 1;
      volatile uint32_t hdtfc6 : 1;
      volatile uint32_t fdtfc6 : 1;
      volatile uint32_t reserved3 : 4;
      volatile uint32_t ferrfc7 : 1;
      volatile uint32_t reserved4 : 1;
      volatile uint32_t dmerrfc7 : 1;
      volatile uint32_t dterrfc7 : 1;
      volatile uint32_t hdtfc7 : 1;
      volatile uint32_t fdtfc7 : 1;
      volatile uint32_t ferrfc8 : 1;
      volatile uint32_t reserved5 : 1;
      volatile uint32_t dmerrfc8 : 1;
      volatile uint32_t dterrfc8 : 1;
      volatile uint32_t hdtfc8 : 1;
      volatile uint32_t fdtfc8 : 1;
      volatile uint32_t reserved6 : 4;
    } clr2_bit;
  };




  volatile uint32_t reserved1[48];




  union
  {
    volatile uint32_t llctrl;
    struct
    {
      volatile uint32_t s1llen : 1;
      volatile uint32_t s2llen : 1;
      volatile uint32_t s3llen : 1;
      volatile uint32_t s4llen : 1;
      volatile uint32_t s5llen : 1;
      volatile uint32_t s6llen : 1;
      volatile uint32_t s7llen : 1;
      volatile uint32_t s8llen : 1;
      volatile uint32_t reserved1 : 24;
    } llctrl_bit;
  };




  volatile uint32_t reserved2[8];




  union
  {
    volatile uint32_t s2dctrl;
    struct
    {
      volatile uint32_t s12den : 1;
      volatile uint32_t s22den : 1;
      volatile uint32_t s32den : 1;
      volatile uint32_t s42den : 1;
      volatile uint32_t s52den : 1;
      volatile uint32_t s62den : 1;
      volatile uint32_t s72den : 1;
      volatile uint32_t s82den : 1;
      volatile uint32_t reserved1 : 24;
    } s2dctrl_bit;
  };




  volatile uint32_t reserved3[17];




  union
  {
    volatile uint32_t muxsel;
    struct
    {
      volatile uint32_t tblsel : 1;
      volatile uint32_t reserved1 : 31;
    }muxsel_bit;
  };




  volatile uint32_t reserved4[12];




  union
  {
    volatile uint32_t muxsyncsts;
    struct
    {
      volatile uint32_t syncovf : 8;
      volatile uint32_t reserved1 : 24;
    }muxsyncsts_bit;
  };




  union
  {
    volatile uint32_t muxsyncclr;
    struct
    {
      volatile uint32_t syncovfc : 8;
      volatile uint32_t reserved1 : 24;
    }muxsyncclr_bit;
  };




  union
  {
    volatile uint32_t muxgsts;
    struct
    {
      volatile uint32_t trgovf : 4;
      volatile uint32_t reserved1 : 28;
    }muxgsts_bit;
  };




  union
  {
    volatile uint32_t muxgclr;
    struct
    {
      volatile uint32_t trgovfc : 4;
      volatile uint32_t reserved1 : 28;
    }muxgclr_bit;
  };

} edma_type;




typedef struct
{



  union
  {
    volatile uint32_t ctrl;
    struct
    {
      volatile uint32_t sen : 1;
      volatile uint32_t dmerrien : 1;
      volatile uint32_t dterrien : 1;
      volatile uint32_t hdtien : 1;
      volatile uint32_t fdtien : 1;
      volatile uint32_t pfctrl : 1;
      volatile uint32_t dtd : 2;
      volatile uint32_t lm : 1;
      volatile uint32_t pincm : 1;
      volatile uint32_t mincm : 1;
      volatile uint32_t pwidth : 2;
      volatile uint32_t mwidth : 2;
      volatile uint32_t pincos : 1;
      volatile uint32_t spl : 2;
      volatile uint32_t dmm : 1;
      volatile uint32_t cm : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t pct : 2;
      volatile uint32_t mct : 2;
      volatile uint32_t reserved2 : 3;
      volatile uint32_t reserved3 : 4;
    } ctrl_bit;
  };



  union
  {
    volatile uint32_t dtcnt;
    struct
    {
      volatile uint32_t cnt : 16;
      volatile uint32_t reserved1 : 16;
    } dtcnt_bit;
  };



  union
  {
    volatile uint32_t paddr;
    struct
    {
      volatile uint32_t paddr : 32;
    } paddr_bit;
  };



  union
  {
    volatile uint32_t m0addr;
    struct
    {
      volatile uint32_t m0addr : 32;
    } m0addr_bit;
  };



  union
  {
    volatile uint32_t m1addr;
    struct
    {
      volatile uint32_t m1addr : 32;
    } m1addr_bit;
  };



  union
  {
    volatile uint32_t fctrl;
    struct
    {
      volatile uint32_t fthsel : 2;
      volatile uint32_t fen : 1;
      volatile uint32_t fsts : 3;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t ferrien : 1;
      volatile uint32_t reserved2 : 24;
    } fctrl_bit;
  };
} edma_stream_type;




typedef struct
{



  union
  {
    volatile uint32_t llp;
    struct
    {
      volatile uint32_t llp : 32;
    } llp_bit;
  };
} edma_stream_link_list_type;




typedef struct
{



  union
  {
    volatile uint32_t s2dcnt;
    struct
    {
      volatile uint32_t xcnt : 16;
      volatile uint32_t ycnt : 16;
    } s2dcnt_bit;
  };



  union
  {
    volatile uint32_t stride;
    struct
    {
      volatile uint32_t srcstd : 16;
      volatile uint32_t dststd : 16;
    } stride_bit;
  };
} edma_stream_2d_type;




typedef struct
{



  union
  {
    volatile uint32_t muxctrl;
    struct
    {
      volatile uint32_t reqsel : 7;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t syncovien : 1;
      volatile uint32_t evtgen : 1;
      volatile uint32_t reserved2 : 6;
      volatile uint32_t syncen : 1;
      volatile uint32_t syncpol : 2;
      volatile uint32_t reqcnt : 5;
      volatile uint32_t syncsel : 5;
      volatile uint32_t reserved3 : 3;
    }muxctrl_bit;
  };
} edmamux_channel_type;




typedef struct
{



  union
  {
    volatile uint32_t gctrl;
    struct
    {
      volatile uint32_t sigsel : 5;
      volatile uint32_t reserved1 : 3;
      volatile uint32_t trgovien : 1;
      volatile uint32_t reserved2 : 7;
      volatile uint32_t gen : 1;
      volatile uint32_t gpol : 2;
      volatile uint32_t greqcnt : 5;
      volatile uint32_t reserved3 : 8;
    }gctrl_bit;
  };
} edmamux_generator_type;
# 1008 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_edma.h"
void edma_reset(edma_stream_type *edma_streamx);
void edma_init(edma_stream_type *edma_streamx, edma_init_type *edma_init_struct);
void edma_default_para_init(edma_init_type *edma_init_struct);
void edma_stream_enable(edma_stream_type *edma_streamx, confirm_state new_state);
void edma_interrupt_enable(edma_stream_type *edma_streamx, uint32_t edma_int, confirm_state new_state);
void edma_peripheral_inc_offset_set(edma_stream_type *edma_streamx, edma_peripheral_inc_offset_type offset);
void edma_flow_controller_enable(edma_stream_type *edma_streamx, confirm_state new_state);
void edma_data_number_set(edma_stream_type *edma_streamx, uint16_t data_number);
uint16_t edma_data_number_get(edma_stream_type *edma_streamx);
void edma_double_buffer_mode_init(edma_stream_type *edma_streamx, uint32_t memory1_addr, edma_memory_type current_memory);
void edma_double_buffer_mode_enable(edma_stream_type *edma_streamx, confirm_state new_state);
void edma_memory_addr_set(edma_stream_type *edma_streamx, uint32_t memory_addr, uint32_t memory_target);
edma_memory_type edma_memory_target_get(edma_stream_type *edma_streamx);
flag_status edma_stream_status_get(edma_stream_type *edma_streamx);
uint8_t edma_fifo_status_get(edma_stream_type *edma_streamx);
flag_status edma_flag_get(uint32_t edma_flag);
void edma_flag_clear(uint32_t edma_flag);


void edma_2d_init(edma_stream_2d_type *edma_streamx_2d, int16_t src_stride, int16_t dst_stride, uint16_t xcnt, uint16_t ycnt);
void edma_2d_enable(edma_stream_2d_type *edma_streamx_2d, confirm_state new_state);


void edma_link_list_init(edma_stream_link_list_type *edma_streamx_ll, uint32_t pointer);
void edma_link_list_enable(edma_stream_link_list_type *edma_streamx_ll, confirm_state new_state);


void edmamux_enable(confirm_state new_state);
void edmamux_init(edmamux_channel_type *edmamux_channelx, edmamux_requst_id_sel_type edmamux_req_id);
void edmamux_sync_default_para_init(edmamux_sync_init_type *edmamux_sync_init_struct);
void edmamux_sync_config(edmamux_channel_type *edmamux_channelx, edmamux_sync_init_type *edmamux_sync_init_struct);
void edmamux_generator_default_para_init(edmamux_gen_init_type *edmamux_gen_init_struct);
void edmamux_generator_config(edmamux_generator_type *edmamux_gen_x, edmamux_gen_init_type *edmamux_gen_init_struct);
void edmamux_sync_interrupt_enable(edmamux_channel_type *edmamux_channelx, confirm_state new_state);
void edmamux_generator_interrupt_enable(edmamux_generator_type *edmamux_gen_x, confirm_state new_state);
flag_status edmamux_sync_flag_get(uint32_t flag);
void edmamux_sync_flag_clear(uint32_t flag);
flag_status edmamux_generator_flag_get(uint32_t flag);
void edmamux_generator_flag_clear(uint32_t flag);
# 151 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_qspi.h" 1
# 67 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_qspi.h"
typedef enum
{
  QSPI_XIPR_SEL_MODED = 0x00,
  QSPI_XIPR_SEL_MODET = 0x01
} qspi_xip_read_sel_type;




typedef enum
{
  QSPI_XIPW_SEL_MODED = 0x00,
  QSPI_XIPW_SEL_MODET = 0x01
} qspi_xip_write_sel_type;




typedef enum
{
  QSPI_BUSY_OFFSET_0 = 0x00,
  QSPI_BUSY_OFFSET_1 = 0x01,
  QSPI_BUSY_OFFSET_2 = 0x02,
  QSPI_BUSY_OFFSET_3 = 0x03,
  QSPI_BUSY_OFFSET_4 = 0x04,
  QSPI_BUSY_OFFSET_5 = 0x05,
  QSPI_BUSY_OFFSET_6 = 0x06,
  QSPI_BUSY_OFFSET_7 = 0x07
} qspi_busy_pos_type;




typedef enum
{
  QSPI_RSTSC_HW_AUTO = 0x00,
  QSPI_RSTSC_SW_ONCE = 0x01
} qspi_read_status_conf_type;




typedef enum
{
  QSPI_OPERATE_MODE_111 = 0x00,
  QSPI_OPERATE_MODE_112 = 0x01,
  QSPI_OPERATE_MODE_114 = 0x02,
  QSPI_OPERATE_MODE_122 = 0x03,
  QSPI_OPERATE_MODE_144 = 0x04,
  QSPI_OPERATE_MODE_222 = 0x05,
  QSPI_OPERATE_MODE_444 = 0x06
} qspi_operate_mode_type;




typedef enum
{
  QSPI_CLK_DIV_2 = 0x00,
  QSPI_CLK_DIV_4 = 0x01,
  QSPI_CLK_DIV_6 = 0x02,
  QSPI_CLK_DIV_8 = 0x03,
  QSPI_CLK_DIV_3 = 0x04,
  QSPI_CLK_DIV_5 = 0x05,
  QSPI_CLK_DIV_10 = 0x06,
  QSPI_CLK_DIV_12 = 0x07
} qspi_clk_div_type;




typedef enum
{
  QSPI_CMD_ADRLEN_0_BYTE = 0x00,
  QSPI_CMD_ADRLEN_1_BYTE = 0x01,
  QSPI_CMD_ADRLEN_2_BYTE = 0x02,
  QSPI_CMD_ADRLEN_3_BYTE = 0x03,
  QSPI_CMD_ADRLEN_4_BYTE = 0x04
} qspi_cmd_adrlen_type;




typedef enum
{
  QSPI_CMD_INSLEN_0_BYTE = 0x00,
  QSPI_CMD_INSLEN_1_BYTE = 0x01,
  QSPI_CMD_INSLEN_2_BYTE = 0x02
} qspi_cmd_inslen_type;




typedef enum
{
  QSPI_XIP_ADDRLEN_3_BYTE = 0x00,
  QSPI_XIP_ADDRLEN_4_BYTE = 0x01
} qspi_xip_addrlen_type;




typedef enum
{
  QSPI_SCK_MODE_0 = 0x00,
  QSPI_SCK_MODE_3 = 0x01
} qspi_clk_mode_type;




typedef enum
{
  QSPI_DMA_FIFO_THOD_WORD08 = 0x00,
  QSPI_DMA_FIFO_THOD_WORD16 = 0x01,
  QSPI_DMA_FIFO_THOD_WORD32 = 0x02
} qspi_dma_fifo_thod_type;




typedef struct
{
  confirm_state pe_mode_enable;
  uint8_t pe_mode_operate_code;
  uint8_t instruction_code;
  qspi_cmd_inslen_type instruction_length;
  uint32_t address_code;
  qspi_cmd_adrlen_type address_length;
  uint32_t data_counter;
  uint8_t second_dummy_cycle_num;
  qspi_operate_mode_type operation_mode;
  qspi_read_status_conf_type read_status_config;
  confirm_state read_status_enable;
  confirm_state write_data_enable;
} qspi_cmd_type;




typedef struct
{
  uint8_t read_instruction_code;
  qspi_xip_addrlen_type read_address_length;
  qspi_operate_mode_type read_operation_mode;
  uint8_t read_second_dummy_cycle_num;
  uint8_t write_instruction_code;
  qspi_xip_addrlen_type write_address_length;
  qspi_operate_mode_type write_operation_mode;
  uint8_t write_second_dummy_cycle_num;
  qspi_xip_write_sel_type write_select_mode;
  uint8_t write_time_counter;
  uint8_t write_data_counter;
  qspi_xip_read_sel_type read_select_mode;
  uint8_t read_time_counter;
  uint8_t read_data_counter;
} qspi_xip_type;




typedef struct
{



  union
  {
    volatile uint32_t cmd_w0;
    struct
    {

      volatile uint32_t spiadr : 32;
    } cmd_w0_bit;
  };




  union
  {
    volatile uint32_t cmd_w1;
    struct
    {
      volatile uint32_t adrlen : 3;
      volatile uint32_t reserved1 : 13;
      volatile uint32_t dum2 : 8;
      volatile uint32_t inslen : 2;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t pemen : 1;
      volatile uint32_t reserved3 : 3;
    } cmd_w1_bit;
  };




  union
  {
    volatile uint32_t cmd_w2;
    struct
    {
      volatile uint32_t dcnt : 32;
    } cmd_w2_bit;
  };




  union
  {
    volatile uint32_t cmd_w3;
    struct
    {
      volatile uint32_t reserved1 : 1;
      volatile uint32_t wen : 1;
      volatile uint32_t rstsen : 1;
      volatile uint32_t rstsc : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t opmode : 3;
      volatile uint32_t reserved3 : 8;
      volatile uint32_t pemopc : 8;
      volatile uint32_t insc : 8;
    } cmd_w3_bit;
  };




  union
  {
    volatile uint32_t ctrl;
    struct
    {
      volatile uint32_t clkdiv : 3;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t sckmode : 1;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t xipidle : 1;
      volatile uint32_t abort : 1;
      volatile uint32_t reserved3 : 7;
      volatile uint32_t busy : 3;
      volatile uint32_t xiprcmdf : 1;
      volatile uint32_t xipsel : 1;
      volatile uint32_t keyen : 1;
      volatile uint32_t reserved4 : 10;
    } ctrl_bit;
  };




  union
  {
    volatile uint32_t actr;
    struct
    {
      volatile uint32_t csdly : 4;
      volatile uint32_t reserved1 : 28;
    } actr_bit;
  };




  union
  {
    volatile uint32_t fifosts;
    struct
    {
      volatile uint32_t txfifordy : 1;
      volatile uint32_t rxfifordy : 1;
      volatile uint32_t reserved1 : 30;
    } fifosts_bit;
  };




  volatile uint32_t reserved1;




  union
  {
    volatile uint32_t ctrl2;
    struct
    {
      volatile uint32_t dmaen : 1;
      volatile uint32_t cmdie : 1;
      volatile uint32_t reserved1 : 6;
      volatile uint32_t txfifo_thod : 2;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t rxfifo_thod : 2;
      volatile uint32_t reserved3 : 18;
    } ctrl2_bit;
  };




  union
  {
    volatile uint32_t cmdsts;
    struct
    {
      volatile uint32_t cmdsts : 1;
      volatile uint32_t reserved1 : 31;
    } cmdsts_bit;
  };




  union
  {
    volatile uint32_t rsts;
    struct
    {
      volatile uint32_t spists : 8;
      volatile uint32_t reserved1 : 24;
    } rsts_bit;
  };




  union
  {
    volatile uint32_t fsize;
    struct
    {
      volatile uint32_t spifsize : 32;
    } fsize_bit;
  };




  union
  {
    volatile uint32_t xip_cmd_w0;
    struct
    {
      volatile uint32_t xipr_dum2 : 8;
      volatile uint32_t xipr_opmode : 3;
      volatile uint32_t xipr_adrlen : 1;
      volatile uint32_t xipr_insc : 8;
      volatile uint32_t reserved1 : 12;
    } xip_cmd_w0_bit;
  };




  union
  {
    volatile uint32_t xip_cmd_w1;
    struct
    {
      volatile uint32_t xipr_dum2 : 8;
      volatile uint32_t xipr_opmode : 3;
      volatile uint32_t xipr_adrlen : 1;
      volatile uint32_t xipr_insc : 8;
      volatile uint32_t reserved1 : 12;
    } xip_cmd_w1_bit;
  };




  union
  {
    volatile uint32_t xip_cmd_w2;
    struct
    {
      volatile uint32_t xipr_dcnt : 6;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t xipr_tcnt : 7;
      volatile uint32_t xipr_sel : 1;
      volatile uint32_t xipw_dcnt : 6;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t xipw_tcnt : 7;
      volatile uint32_t xipw_sel : 1;
    } xip_cmd_w2_bit;
  };




  union
  {
    volatile uint32_t xip_cmd_w3;
    struct
    {
      volatile uint32_t bypassc : 1;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t csts : 1;
      volatile uint32_t reserved2 : 28;
    } xip_cmd_w3_bit;
  };




  volatile uint32_t reserved2[4];




  union
  {
    volatile uint32_t rev;
    struct
    {
      volatile uint32_t rev : 32;
    } rev_bit;
  };




  volatile uint32_t reserved3[43];




  union
  {
    volatile uint8_t dt_u8;
    volatile uint16_t dt_u16;
    volatile uint32_t dt;
    struct
    {
      volatile uint32_t dt : 32;
    } dt_bit;
  };

} qspi_type;
# 519 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_qspi.h"
void qspi_encryption_enable(qspi_type* qspi_x, confirm_state new_state);
void qspi_sck_mode_set(qspi_type* qspi_x, qspi_clk_mode_type new_mode);
void qspi_clk_division_set(qspi_type* qspi_x, qspi_clk_div_type new_clkdiv);
void qspi_xip_cache_bypass_set(qspi_type* qspi_x, confirm_state new_state);
void qspi_interrupt_enable(qspi_type* qspi_x, confirm_state new_state);
flag_status qspi_flag_get(qspi_type* qspi_x, uint32_t flag);
void qspi_flag_clear(qspi_type* qspi_x, uint32_t flag);
void qspi_dma_rx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
void qspi_dma_tx_threshold_set(qspi_type* qspi_x, qspi_dma_fifo_thod_type new_threshold);
void qspi_dma_enable(qspi_type* qspi_x, confirm_state new_state);
void qspi_busy_config(qspi_type* qspi_x, qspi_busy_pos_type busy_pos);
void qspi_xip_enable(qspi_type* qspi_x, confirm_state new_state);
void qspi_cmd_operation_kick(qspi_type* qspi_x, qspi_cmd_type* qspi_cmd_struct);
void qspi_xip_init(qspi_type* qspi_x, qspi_xip_type* xip_init_struct);
uint8_t qspi_byte_read(qspi_type* qspi_x);
uint16_t qspi_half_word_read(qspi_type* qspi_x);
uint32_t qspi_word_read(qspi_type* qspi_x);
void qspi_word_write(qspi_type* qspi_x, uint32_t value);
void qspi_half_word_write(qspi_type* qspi_x, uint16_t value);
void qspi_byte_write(qspi_type* qspi_x, uint8_t value);
# 154 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_scfg.h" 1
# 57 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_scfg.h"
typedef enum
{
  SCFG_XMC_SWAP_NONE = 0x00,
  SCFG_XMC_SWAP_MODE1 = 0x01,
  SCFG_XMC_SWAP_MODE2 = 0x02,
  SCFG_XMC_SWAP_MODE3 = 0x03
} scfg_xmc_swap_type;




typedef enum
{
  SCFG_IR_SOURCE_TMR10 = 0x00,
  SCFG_IR_SOURCE_USART1 = 0x01,
  SCFG_IR_SOURCE_USART2 = 0x02
} scfg_ir_source_type;




typedef enum
{
  SCFG_IR_POLARITY_NO_AFFECTE = 0x00,
  SCFG_IR_POLARITY_REVERSE = 0x01
} scfg_ir_polarity_type;




typedef enum
{
  SCFG_MEM_MAP_MAIN_MEMORY = 0x00,
  SCFG_MEM_MAP_BOOT_MEMORY = 0x01,
  SCFG_MEM_MAP_XMC_BANK1 = 0x02,
  SCFG_MEM_MAP_INTERNAL_SRAM = 0x03,
  SCFG_MEM_MAP_XMC_SDRAM_BANK1 = 0x04
} scfg_mem_map_type;




typedef enum
{
  SCFG_PINS_SOURCE0 = 0x00,
  SCFG_PINS_SOURCE1 = 0x01,
  SCFG_PINS_SOURCE2 = 0x02,
  SCFG_PINS_SOURCE3 = 0x03,
  SCFG_PINS_SOURCE4 = 0x04,
  SCFG_PINS_SOURCE5 = 0x05,
  SCFG_PINS_SOURCE6 = 0x06,
  SCFG_PINS_SOURCE7 = 0x07,
  SCFG_PINS_SOURCE8 = 0x08,
  SCFG_PINS_SOURCE9 = 0x09,
  SCFG_PINS_SOURCE10 = 0x0A,
  SCFG_PINS_SOURCE11 = 0x0B,
  SCFG_PINS_SOURCE12 = 0x0C,
  SCFG_PINS_SOURCE13 = 0x0D,
  SCFG_PINS_SOURCE14 = 0x0E,
  SCFG_PINS_SOURCE15 = 0x0F
} scfg_pins_source_type;




typedef enum
{
  SCFG_PORT_SOURCE_GPIOA = 0x00,
  SCFG_PORT_SOURCE_GPIOB = 0x01,
  SCFG_PORT_SOURCE_GPIOC = 0x02,
  SCFG_PORT_SOURCE_GPIOD = 0x03,
  SCFG_PORT_SOURCE_GPIOE = 0x04,
  SCFG_PORT_SOURCE_GPIOF = 0x05,
  SCFG_PORT_SOURCE_GPIOG = 0x06,
  SCFG_PORT_SOURCE_GPIOH = 0x07
} scfg_port_source_type;




typedef enum
{
  SCFG_EMAC_SELECT_MII = 0x00,
  SCFG_EMAC_SELECT_RMII = 0x01
} scfg_emac_interface_type;




typedef enum
{
  SCFG_ULTRA_DRIVEN_PB3 = (((0x2C) << 16) | (0 & 0x1f)),
  SCFG_ULTRA_DRIVEN_PB9 = (((0x2C) << 16) | (1 & 0x1f)),
  SCFG_ULTRA_DRIVEN_PB10 = (((0x2C) << 16) | (2 & 0x1f)),
  SCFG_ULTRA_DRIVEN_PD12 = (((0x2C) << 16) | (5 & 0x1f)),
  SCFG_ULTRA_DRIVEN_PD13 = (((0x2C) << 16) | (6 & 0x1f)),
  SCFG_ULTRA_DRIVEN_PD14 = (((0x2C) << 16) | (7 & 0x1f)),
  SCFG_ULTRA_DRIVEN_PD15 = (((0x2C) << 16) | (8 & 0x1f)),
  SCFG_ULTRA_DRIVEN_PF14 = (((0x2C) << 16) | (9 & 0x1f)),
  SCFG_ULTRA_DRIVEN_PF15 = (((0x2C) << 16) | (10 & 0x1f))
} scfg_ultra_driven_pins_type;




typedef struct
{



  union
  {
    volatile uint32_t cfg1;
    struct
    {
      volatile uint32_t mem_map_sel : 3;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t ir_pol : 1;
      volatile uint32_t ir_src_sel : 2;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t swap_xmc : 2;
      volatile uint32_t reserved3 : 20;
    } cfg1_bit;
  };




  union
  {
    volatile uint32_t cfg2;
    struct
    {
      volatile uint32_t reserved1 : 23;
      volatile uint32_t mii_rmii_sel : 1;
      volatile uint32_t reserved2 : 8;
    } cfg2_bit;
  };




  union
  {
    volatile uint32_t exintc1;
    struct
    {
      volatile uint32_t exint0 : 4;
      volatile uint32_t exint1 : 4;
      volatile uint32_t exint2 : 4;
      volatile uint32_t exint3 : 4;
      volatile uint32_t reserved1 : 16;
    } exintc1_bit;
  };




  union
  {
    volatile uint32_t exintc2;
    struct
    {
      volatile uint32_t exint4 : 4;
      volatile uint32_t exint5 : 4;
      volatile uint32_t exint6 : 4;
      volatile uint32_t exint7 : 4;
      volatile uint32_t reserved1 : 16;
    } exintc2_bit;
  };




  union
  {
    volatile uint32_t exintc3;
    struct
    {
      volatile uint32_t exint8 : 4;
      volatile uint32_t exint9 : 4;
      volatile uint32_t exint10 : 4;
      volatile uint32_t exint11 : 4;
      volatile uint32_t reserved1 : 16;
    } exintc3_bit;
  };




  union
  {
    volatile uint32_t exintc4;
    struct
    {
      volatile uint32_t exint12 : 4;
      volatile uint32_t exint13 : 4;
      volatile uint32_t exint14 : 4;
      volatile uint32_t exint15 : 4;
      volatile uint32_t reserved1 : 16;
    } exintc4_bit;
  };




  volatile uint32_t reserved1[5];




  union
  {
    volatile uint32_t uhdrv;
    struct
    {
      volatile uint32_t pb3_uh : 1;
      volatile uint32_t pb9_uh : 1;
      volatile uint32_t pb10_uh : 1;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t pd12_uh : 1;
      volatile uint32_t pd13_uh : 1;
      volatile uint32_t pd14_uh : 1;
      volatile uint32_t pd15_uh : 1;
      volatile uint32_t pf14_uh : 1;
      volatile uint32_t pf15_uh : 1;
      volatile uint32_t reserved2 : 21;
    } uhdrv_bit;
  };

} scfg_type;
# 299 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_scfg.h"
void scfg_reset(void);
void scfg_xmc_mapping_swap_set(scfg_xmc_swap_type xmc_swap);
void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity);
void scfg_mem_map_set(scfg_mem_map_type mem_map);
void scfg_emac_interface_set(scfg_emac_interface_type mode);
void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source);
void scfg_pins_ultra_driven_enable(scfg_ultra_driven_pins_type value, confirm_state new_state);
# 157 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_emac.h" 1
# 281 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_emac.h"
typedef enum
{
  EMAC_AUTO_NEGOTIATION_OFF = 0x00,
  EMAC_AUTO_NEGOTIATION_ON = 0x01
} emac_auto_negotiation_type;




typedef enum
{
  EMAC_BACKOFF_LIMIT_0 = 0x00,
  EMAC_BACKOFF_LIMIT_1 = 0x01,
  EMAC_BACKOFF_LIMIT_2 = 0x02,
  EMAC_BACKOFF_LIMIT_3 = 0x03
} emac_bol_type;




typedef enum
{
  EMAC_HALF_DUPLEX = 0x00,
  EMAC_FULL_DUPLEX = 0x01
} emac_duplex_type;




typedef enum
{
  EMAC_SPEED_10MBPS = 0x00,
  EMAC_SPEED_100MBPS = 0x01
} emac_speed_type;




typedef enum
{
  EMAC_INTERFRAME_GAP_96BIT = 0x00,
  EMAC_INTERFRAME_GAP_88BIT = 0x01,
  EMAC_INTERFRAME_GAP_80BIT = 0x02,
  EMAC_INTERFRAME_GAP_72BIT = 0x03,
  EMAC_INTERFRAME_GAP_64BIT = 0x04,
  EMAC_INTERFRAME_GAP_56BIT = 0x05,
  EMAC_INTERFRAME_GAP_48BIT = 0x06,
  EMAC_INTERFRAME_GAP_40BIT = 0x07
} emac_intergrame_gap_type;




typedef enum
{
  EMAC_CLOCK_RANGE_60_TO_100 = 0x00,
  EMAC_CLOCK_RANGE_100_TO_150 = 0x01,
  EMAC_CLOCK_RANGE_20_TO_35 = 0x02,
  EMAC_CLOCK_RANGE_35_TO_60 = 0x03,
  EMAC_CLOCK_RANGE_150_TO_250 = 0x04,
  EMAC_CLOCK_RANGE_250_TO_288 = 0x05
} emac_clock_range_type;




typedef enum
{
  EMAC_CONTROL_FRAME_PASSING_NO = 0x00,
  EMAC_CONTROL_FRAME_PASSING_ALL = 0x02,
  EMAC_CONTROL_FRAME_PASSING_MATCH = 0x03
} emac_control_frames_filter_type;




typedef enum
{
  EMAC_PAUSE_4_SLOT_TIME = 0x00,
  EMAC_PAUSE_28_SLOT_TIME = 0x01,
  EMAC_PAUSE_144_SLOT_TIME = 0x02,
  EMAC_PAUSE_256_SLOT_TIME = 0x03
} emac_pause_slot_threshold_type;




typedef enum
{
  EMAC_INTERRUPT_PMT_MASK = 0x00,
  EMAC_INTERRUPT_TST_MASK = 0x01
} emac_interrupt_mask_type;




typedef enum
{
  EMAC_ADDRESS_FILTER_1 = 0x01,
  EMAC_ADDRESS_FILTER_2 = 0x02,
  EMAC_ADDRESS_FILTER_3 = 0x03
} emac_address_type;




typedef enum
{
  EMAC_DESTINATION_FILTER = 0x00,
  EMAC_SOURCE_FILTER = 0x01
} emac_address_filter_type;




typedef enum
{
  EMAC_ADDRESS_MASK_8L0 = 0x01,
  EMAC_ADDRESS_MASK_15L8 = 0x02,
  EMAC_ADDRESS_MASK_23L16 = 0x04,
  EMAC_ADDRESS_MASK_31L24 = 0x08,
  EMAC_ADDRESS_MASK_7H0 = 0x10,
  EMAC_ADDRESS_MASK_15H8 = 0x20
} emac_address_mask_type;




typedef enum
{
  EMAC_DMA_1_RX_1_TX = 0x00,
  EMAC_DMA_2_RX_1_TX = 0x01,
  EMAC_DMA_3_RX_1_TX = 0x02,
  EMAC_DMA_4_RX_1_TX = 0x03
} emac_dma_rx_tx_ratio_type;




typedef enum
{
  EMAC_DMA_PBL_1 = 0x01,
  EMAC_DMA_PBL_2 = 0x02,
  EMAC_DMA_PBL_4 = 0x04,
  EMAC_DMA_PBL_8 = 0x08,
  EMAC_DMA_PBL_16 = 0x10,
  EMAC_DMA_PBL_32 = 0x20
} emac_dma_pbl_type;




typedef enum
{
  EMAC_DMA_TRANSMIT = 0x00,
  EMAC_DMA_RECEIVE = 0x01
} emac_dma_tx_rx_type;




typedef enum
{
  EMAC_DMA_RX_RESET_STOP_COMMAND = 0x00,
  EMAC_DMA_RX_FETCH_DESCRIPTOR = 0x01,
  EMAC_DMA_RX_WAITING_PACKET = 0x03,
  EMAC_DMA_RX_DESCRIPTOR_UNAVAILABLE = 0x04,
  EMAC_DMA_RX_CLOSE_DESCRIPTOR = 0x05,
  EMAC_DMA_RX_FIFO_TO_HOST = 0x07
} emac_dma_receive_process_status_type;




typedef enum
{
  EMAC_DMA_TX_RESET_STOP_COMMAND = 0x00,
  EMAC_DMA_TX_FETCH_DESCRIPTOR = 0x01,
  EMAC_DMA_TX_WAITING_FOR_STATUS = 0x02,
  EMAC_DMA_TX_HOST_TO_FIFO = 0x03,
  EMAC_DMA_TX_DESCRIPTOR_UNAVAILABLE = 0x06,
  EMAC_DMA_TX_CLOSE_DESCRIPTOR = 0x07
} emac_dma_transmit_process_status_type;




typedef enum
{
  EMAC_DMA_OPS_START_STOP_RECEIVE = 0x00,
  EMAC_DMA_OPS_SECOND_FRAME = 0x01,
  EMAC_DMA_OPS_FORWARD_UNDERSIZED = 0x02,
  EMAC_DMA_OPS_FORWARD_ERROR = 0x03,
  EMAC_DMA_OPS_START_STOP_TRANSMIT = 0x04,
  EMAC_DMA_OPS_FLUSH_TRANSMIT_FIFO = 0x05,
  EMAC_DMA_OPS_TRANSMIT_STORE_FORWARD = 0x06,
  EMAC_DMA_OPS_RECEIVE_FLUSH_DISABLE = 0x07,
  EMAC_DMA_OPS_RECEIVE_STORE_FORWARD = 0x08,
  EMAC_DMA_OPS_DROP_ERROR_DISABLE = 0x09
} emac_dma_operations_type;




typedef enum
{
  EMAC_DMA_RX_THRESHOLD_64_BYTES = 0x00,
  EMAC_DMA_RX_THRESHOLD_32_BYTES = 0x01,
  EMAC_DMA_RX_THRESHOLD_96_BYTES = 0x02,
  EMAC_DMA_RX_THRESHOLD_128_BYTES = 0x03
} emac_dma_receive_threshold_type;




typedef enum
{
  EMAC_DMA_TX_THRESHOLD_64_BYTES = 0x00,
  EMAC_DMA_TX_THRESHOLD_128_BYTES = 0x01,
  EMAC_DMA_TX_THRESHOLD_192_BYTES = 0x02,
  EMAC_DMA_TX_THRESHOLD_256_BYTES = 0x03,
  EMAC_DMA_TX_THRESHOLD_40_BYTES = 0x04,
  EMAC_DMA_TX_THRESHOLD_32_BYTES = 0x05,
  EMAC_DMA_TX_THRESHOLD_24_BYTES = 0x06,
  EMAC_DMA_TX_THRESHOLD_16_BYTES = 0x07
} emac_dma_transmit_threshold_type;




typedef enum
{
  EMAC_DMA_INTERRUPT_TX = 0x00,
  EMAC_DMA_INTERRUPT_TX_STOP = 0x01,
  EMAC_DMA_INTERRUPT_TX_UNAVAILABLE = 0x02,
  EMAC_DMA_INTERRUPT_TX_JABBER = 0x03,
  EMAC_DMA_INTERRUPT_RX_OVERFLOW = 0x04,
  EMAC_DMA_INTERRUPT_TX_UNDERFLOW = 0x05,
  EMAC_DMA_INTERRUPT_RX = 0x06,
  EMAC_DMA_INTERRUPT_RX_UNAVAILABLE = 0x07,
  EMAC_DMA_INTERRUPT_RX_STOP = 0x08,
  EMAC_DMA_INTERRUPT_RX_TIMEOUT = 0x09,
  EMAC_DMA_INTERRUPT_TX_EARLY = 0x0A,
  EMAC_DMA_INTERRUPT_FATAL_BUS_ERROR = 0x0B,
  EMAC_DMA_INTERRUPT_RX_EARLY = 0x0C,
  EMAC_DMA_INTERRUPT_ABNORMAL_SUMMARY = 0x0D,
  EMAC_DMA_INTERRUPT_NORMAL_SUMMARY = 0x0E
} emac_dma_interrupt_type;




typedef enum
{
  EMAC_DMA_TX_DESCRIPTOR = 0x00,
  EMAC_DMA_RX_DESCRIPTOR = 0x01,
  EMAC_DMA_TX_BUFFER = 0x02,
  EMAC_DMA_RX_BUFFER = 0x03
} emac_dma_transfer_address_type;




typedef enum
{
  EMAC_PTP_NORMAL_CLOCK = 0x00,
  EMAC_PTP_BOUNDARY_CLOCK = 0x01,
  EMAC_PTP_END_TO_END_CLOCK = 0x02,
  EMAC_PTP_PEER_TO_PEER_CLOCK = 0x03
} emac_ptp_clock_node_type;




typedef enum
{
  EMAC_PTP_SECOND_OVERFLOW = 0x00,
  EMAC_PTP_TARGET_TIME_REACH = 0x01
} emac_ptp_timestamp_status_type;




typedef enum
{
  EMAC_PTP_PPS_1HZ = 0x00,
  EMAC_PTP_PPS_2HZ = 0x01,
  EMAC_PTP_PPS_4HZ = 0x02,
  EMAC_PTP_PPS_8HZ = 0x03,
  EMAC_PTP_PPS_16HZ = 0x04,
  EMAC_PTP_PPS_32HZ = 0x05,
  EMAC_PTP_PPS_64HZ = 0x06,
  EMAC_PTP_PPS_128HZ = 0x07,
  EMAC_PTP_PPS_256HZ = 0x08,
  EMAC_PTP_PPS_512HZ = 0x09,
  EMAC_PTP_PPS_1024HZ = 0x0A,
  EMAC_PTP_PPS_2048HZ = 0x0B,
  EMAC_PTP_PPS_4096HZ = 0x0C,
  EMAC_PTP_PPS_8192HZ = 0x0D,
  EMAC_PTP_PPS_16384HZ = 0x0E,
  EMAC_PTP_PPS_32768HZ = 0x0F
} emac_ptp_pps_control_type;




typedef struct
{
  emac_auto_negotiation_type auto_nego;
  confirm_state deferral_check;
  emac_bol_type back_off_limit;
  confirm_state auto_pad_crc_strip;
  confirm_state retry_disable;
  confirm_state ipv4_checksum_offload;
  emac_duplex_type duplex_mode;
  confirm_state loopback_mode;
  confirm_state receive_own_disable;
  emac_speed_type fast_ethernet_speed;
  confirm_state carrier_sense_disable;
  emac_intergrame_gap_type interframe_gap;
  confirm_state jabber_disable;
  confirm_state watchdog_disable;
} emac_control_config_type;




typedef struct
{
  confirm_state aab_enable;
  confirm_state usp_enable;
  emac_dma_pbl_type rx_dma_pal;
  confirm_state fb_enable;
  emac_dma_pbl_type tx_dma_pal;
  uint8_t desc_skip_length;
  confirm_state da_enable;
  emac_dma_rx_tx_ratio_type priority_ratio;
  confirm_state dt_disable;
  confirm_state rsf_enable;
  confirm_state flush_rx_disable;
  confirm_state tsf_enable;
  emac_dma_transmit_threshold_type tx_threshold;
  confirm_state fef_enable;
  confirm_state fugf_enable;
  emac_dma_receive_threshold_type rx_threshold;
  confirm_state osf_enable;
} emac_dma_config_type;




typedef struct {
  uint32_t status;
  uint32_t controlsize;
  uint32_t buf1addr;
  uint32_t buf2nextdescaddr;
} emac_dma_desc_type;




typedef struct
{



  union
  {
    volatile uint32_t ctrl;
    struct
    {
      volatile uint32_t reserved1 : 2;
      volatile uint32_t re : 1;
      volatile uint32_t te : 1;
      volatile uint32_t dc : 1;
      volatile uint32_t bl : 2;
      volatile uint32_t acs : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t dr : 1;
      volatile uint32_t ipc : 1;
      volatile uint32_t dm : 1;
      volatile uint32_t lm : 1;
      volatile uint32_t dro : 1;
      volatile uint32_t fes : 1;
      volatile uint32_t reserved3 : 1;
      volatile uint32_t dcs : 1;
      volatile uint32_t ifg : 3;
      volatile uint32_t reserved4 : 2;
      volatile uint32_t jd : 1;
      volatile uint32_t wd : 1;
      volatile uint32_t reserved5 : 8;
    } ctrl_bit;
  };




  union
  {
    volatile uint32_t frmf;
    struct
    {
      volatile uint32_t pr : 1;
      volatile uint32_t huc : 1;
      volatile uint32_t hmc : 1;
      volatile uint32_t daif : 1;
      volatile uint32_t pmc : 1;
      volatile uint32_t dbf : 1;
      volatile uint32_t pcf : 2;
      volatile uint32_t saif : 1;
      volatile uint32_t saf : 1;
      volatile uint32_t hpf : 1;
      volatile uint32_t reserved1 : 20;
      volatile uint32_t ra : 1;
    } frmf_bit;
  };




  union
  {
    volatile uint32_t hth;
    struct
    {
      volatile uint32_t hth : 32;
    } hth_bit;
  };




  union
  {
    volatile uint32_t htl;
    struct
    {
      volatile uint32_t htl : 32;
    } htl_bit;
  };




  union
  {
    volatile uint32_t miiaddr;
    struct
    {
      volatile uint32_t mb : 1;
      volatile uint32_t mw : 1;
      volatile uint32_t cr : 4;
      volatile uint32_t mii : 5;
      volatile uint32_t pa : 5;
      volatile uint32_t reserved1 : 16;
    } miiaddr_bit;
  };




  union
  {
    volatile uint32_t miidt;
    struct
    {
      volatile uint32_t md : 16;
      volatile uint32_t reserved1 : 16;
    } miidt_bit;
  };




  union
  {
    volatile uint32_t fctrl;
    struct
    {
      volatile uint32_t fcbbpa : 1;
      volatile uint32_t etf : 1;
      volatile uint32_t erf : 1;
      volatile uint32_t dup : 1;
      volatile uint32_t plt : 2;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t dzqp : 1;
      volatile uint32_t reserved2 : 8;
      volatile uint32_t pt : 16;
    } fctrl_bit;
  };




  union
  {
    volatile uint32_t vlt;
    struct
    {
      volatile uint32_t vti : 16;
      volatile uint32_t etv : 1;
      volatile uint32_t reserved1 : 15;
    } vlt_bit;
  };




  volatile uint32_t reserved1[2];




  volatile uint32_t rwff;




  union
  {
    volatile uint32_t pmtctrlsts;
    struct
    {
      volatile uint32_t pd : 1;
      volatile uint32_t emp : 1;
      volatile uint32_t erwf : 1;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t rmp : 1;
      volatile uint32_t rrwf : 1;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t guc : 1;
      volatile uint32_t reserved3 : 21;
      volatile uint32_t rwffpr : 1;
    } pmtctrlsts_bit;
  };




  volatile uint32_t reserved2[2];




  union
  {
    volatile uint32_t ists;
    struct
    {
      volatile uint32_t reserved1 : 3;
      volatile uint32_t pis : 1;
      volatile uint32_t mis : 1;
      volatile uint32_t mris : 1;
      volatile uint32_t mtis : 1;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t tis : 1;
      volatile uint32_t reserved3 : 22;
    } ists_bit;
  };




  union
  {
    volatile uint32_t imr;
    struct
    {
      volatile uint32_t reserved1 : 3;
      volatile uint32_t pim : 1;
      volatile uint32_t reserved2 : 5;
      volatile uint32_t tim : 1;
      volatile uint32_t reserved3 : 22;
    } imr_bit;
  };




  union
  {
    volatile uint32_t a0h;
    struct
    {
      volatile uint32_t ma0h : 16;
      volatile uint32_t reserved1 : 15;
      volatile uint32_t ae : 1;
    } a0h_bit;
  };




  union
  {
    volatile uint32_t a0l;
    struct
    {
      volatile uint32_t ma0l : 32;
    } a0l_bit;
  };




  union
  {
    volatile uint32_t a1h;
    struct
    {
      volatile uint32_t ma1h : 16;
      volatile uint32_t reserved1 : 8;
      volatile uint32_t mbc : 6;
      volatile uint32_t sa : 1;
      volatile uint32_t ae : 1;
    } a1h_bit;
  };




  union
  {
    volatile uint32_t a1l;
    struct
    {
      volatile uint32_t ma1l : 32;
    } a1l_bit;
  };




  union
  {
    volatile uint32_t a2h;
    struct
    {
      volatile uint32_t ma2h : 16;
      volatile uint32_t reserved1 : 8;
      volatile uint32_t mbc : 6;
      volatile uint32_t sa : 1;
      volatile uint32_t ae : 1;
    } a2h_bit;
  };




  union
  {
    volatile uint32_t a2l;
    struct
    {
      volatile uint32_t ma2l : 32;
    } a2l_bit;
  };




  union
  {
    volatile uint32_t a3h;
    struct
    {
      volatile uint32_t ma3h : 16;
      volatile uint32_t reserved1 : 8;
      volatile uint32_t mbc : 6;
      volatile uint32_t sa : 1;
      volatile uint32_t ae : 1;
    } a3h_bit;
  };




  union
  {
    volatile uint32_t a3l;
    struct
    {
      volatile uint32_t ma3l : 32;
    } a3l_bit;
  };
} emac_type;




typedef struct
{



  union
  {
    volatile uint32_t ctrl;
    struct
    {
      volatile uint32_t rc : 1;
      volatile uint32_t scr : 1;
      volatile uint32_t rr : 1;
      volatile uint32_t fmc : 1;
      volatile uint32_t reserved1 : 28;
    } ctrl_bit;
  };




  union
  {
    volatile uint32_t ri;
    struct
    {
      volatile uint32_t reserved1 : 5;
      volatile uint32_t rfce : 1;
      volatile uint32_t rfae : 1;
      volatile uint32_t reserved2 : 10;
      volatile uint32_t rguf : 1;
      volatile uint32_t reserved3 : 14;
    } ri_bit;
  };




  union
  {
    volatile uint32_t ti;
    struct
    {
      volatile uint32_t reserved1 : 14;
      volatile uint32_t tscgfci : 1;
      volatile uint32_t tgfmsc : 1;
      volatile uint32_t reserved2 : 5;
      volatile uint32_t tgf : 1;
      volatile uint32_t reserved3 : 10;
    } ti_bit;
  };




  union
  {
    volatile uint32_t rim;
    struct
    {
      volatile uint32_t reserved1 : 5;
      volatile uint32_t rcefcim : 1;
      volatile uint32_t raefacim : 1;
      volatile uint32_t reserved2 : 10;
      volatile uint32_t rugfcim : 1;
      volatile uint32_t reserved3 : 14;
    } rim_bit;
  };




  union
  {
    volatile uint32_t tim;
    struct
    {
      volatile uint32_t reserved1 : 14;
      volatile uint32_t tscgfcim : 1;
      volatile uint32_t tmcgfcim : 1;
      volatile uint32_t reserved2 : 5;
      volatile uint32_t tgfcim : 1;
      volatile uint32_t reserved3 : 10;
    } tim_bit;
  };




  volatile uint32_t reserved1[14];




  union
  {
    volatile uint32_t tfscc;
    struct
    {
      volatile uint32_t tgfscc : 32;
    } tfscc_bit;
  };




  union
  {
    volatile uint32_t tfmscc;
    struct
    {
      volatile uint32_t tgfmscc : 32;
    } tfmscc_bit;
  };




  volatile uint32_t reserved2[5];




  union
  {
    volatile uint32_t tfcnt;
    struct
    {
      volatile uint32_t tgfc : 32;
    } tfcnt_bit;
  };




  volatile uint32_t reserved3[10];




  union
  {
    volatile uint32_t rfcecnt;
    struct
    {
      volatile uint32_t rfcec : 32;
    } rfcecnt_bit;
  };




  union
  {
    volatile uint32_t rfaecnt;
    struct
    {
      volatile uint32_t rfaec : 32;
    } rfaecnt_bit;
  };




  volatile uint32_t reserved4[10];




  union
  {
    volatile uint32_t rgufcnt;
    struct
    {
      volatile uint32_t rgufc : 32;
    } rgufcnt_bit;
  };
} emac_mmc_type;




typedef struct
{



  union
  {
    volatile uint32_t tsctrl;
    struct
    {
      volatile uint32_t te : 1;
      volatile uint32_t tfcu : 1;
      volatile uint32_t ti : 1;
      volatile uint32_t tu : 1;
      volatile uint32_t tite : 1;
      volatile uint32_t aru : 1;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t etaf : 1;
      volatile uint32_t tdbrc : 1;
      volatile uint32_t eppv2f : 1;
      volatile uint32_t eppef : 1;
      volatile uint32_t eppfsip6u : 1;
      volatile uint32_t eppfsip4u : 1;
      volatile uint32_t etsfem : 1;
      volatile uint32_t esfmrtm : 1;
      volatile uint32_t sppfts : 2;
      volatile uint32_t emafpff : 1;
      volatile uint32_t reserved2 : 13;
    } tsctrl_bit;
  };




  union
  {
    volatile uint32_t ssinc;
    struct
    {
      volatile uint32_t ssiv : 8;
      volatile uint32_t reserved1 : 24;
    } ssinc_bit;
  };




  union
  {
    volatile uint32_t tsh;
    struct
    {
      volatile uint32_t ts : 32;
    } tsh_bit;
  };




  union
  {
    volatile uint32_t tsl;
    struct
    {
      volatile uint32_t tss : 31;
      volatile uint32_t ast : 1;
    } tsl_bit;
  };




  union
  {
    volatile uint32_t tshud;
    struct
    {
      volatile uint32_t ts : 32;
    } tshud_bit;
  };




  union
  {
    volatile uint32_t tslud;
    struct
    {
      volatile uint32_t tss : 31;
      volatile uint32_t ast : 1;
    } tslud_bit;
  };




  union
  {
    volatile uint32_t tsad;
    struct
    {
      volatile uint32_t tar : 32;
    } tsad_bit;
  };




  union
  {
    volatile uint32_t tth;
    struct
    {
      volatile uint32_t ttsr : 32;
    } tth_bit;
  };




  union
  {
    volatile uint32_t ttl;
    struct
    {
      volatile uint32_t ttlr : 32;
    } ttl_bit;
  };




  volatile uint32_t reserved1;




  union
  {
    volatile uint32_t tssr;
    struct
    {
      volatile uint32_t tso : 1;
      volatile uint32_t tttr : 1;
      volatile uint32_t reserved1 : 30;
    } tssr_bit;
  };




  union
  {
    volatile uint32_t ppscr;
    struct
    {
      volatile uint32_t pofc : 4;
      volatile uint32_t reserved1 : 28;
    } ppscr_bit;
  };
} emac_ptp_type;




typedef struct
{



  union
  {
    volatile uint32_t bm;
    struct
    {
      volatile uint32_t swr : 1;
      volatile uint32_t da : 1;
      volatile uint32_t dsl : 5;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t pbl : 6;
      volatile uint32_t pr : 2;
      volatile uint32_t fb : 1;
      volatile uint32_t rdp : 6;
      volatile uint32_t usp : 1;
      volatile uint32_t pblx8 : 1;
      volatile uint32_t aab : 1;
      volatile uint32_t reserved2 : 6;
    } bm_bit;
  };




  union
  {
    volatile uint32_t tpd;
    struct
    {
      volatile uint32_t tpd : 32;
    } tpd_bit;
  };




  union
  {
    volatile uint32_t rpd;
    struct
    {
      volatile uint32_t rpd : 32;
    } rpd_bit;
  };




  union
  {
    volatile uint32_t rdladdr;
    struct
    {
      volatile uint32_t srl : 32;
    } rdladdr_bit;
  };




  union
  {
    volatile uint32_t tdladdr;
    struct
    {
      volatile uint32_t stl : 32;
    } tdladdr_bit;
  };




  union
  {
    volatile uint32_t sts;
    struct
    {
      volatile uint32_t ti : 1;
      volatile uint32_t tps : 1;
      volatile uint32_t tbu : 1;
      volatile uint32_t tjt : 1;
      volatile uint32_t ovf : 1;
      volatile uint32_t unf : 1;
      volatile uint32_t ri : 1;
      volatile uint32_t rbu : 1;
      volatile uint32_t rps : 1;
      volatile uint32_t rwt : 1;
      volatile uint32_t eti : 1;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t fbei : 1;
      volatile uint32_t eri : 1;
      volatile uint32_t ais : 1;
      volatile uint32_t nis : 1;
      volatile uint32_t rs : 3;
      volatile uint32_t ts : 3;
      volatile uint32_t eb : 3;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t mmi : 1;
      volatile uint32_t mpi : 1;
      volatile uint32_t tti : 1;
      volatile uint32_t reserved3 : 2;
    } sts_bit;
  };




  union
  {
    volatile uint32_t opm;
    struct
    {
      volatile uint32_t reserved1 : 1;
      volatile uint32_t ssr : 1;
      volatile uint32_t osf : 1;
      volatile uint32_t rtc : 2;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t fugf : 1;
      volatile uint32_t fef : 1;
      volatile uint32_t reserved3 : 5;
      volatile uint32_t sstc : 1;
      volatile uint32_t ttc : 3;
      volatile uint32_t reserved4 : 3;
      volatile uint32_t ftf : 1;
      volatile uint32_t tsf : 1;
      volatile uint32_t reserved5 : 2;
      volatile uint32_t dfrf : 1;
      volatile uint32_t rsf : 1;
      volatile uint32_t dt : 1;
      volatile uint32_t reserved6 : 5;
    } opm_bit;
  };




  union
  {
    volatile uint32_t ie;
    struct
    {
      volatile uint32_t tie : 1;
      volatile uint32_t tse : 1;
      volatile uint32_t tue : 1;
      volatile uint32_t tje : 1;
      volatile uint32_t ove : 1;
      volatile uint32_t une : 1;
      volatile uint32_t rie : 1;
      volatile uint32_t rbue : 1;
      volatile uint32_t rse : 1;
      volatile uint32_t rwte : 1;
      volatile uint32_t eie : 1;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t fbee : 1;
      volatile uint32_t ere : 1;
      volatile uint32_t aie : 1;
      volatile uint32_t nie : 1;
      volatile uint32_t reserved2 : 15;
    } ie_bit;
  };




  union
  {
    volatile uint32_t mfbocnt;
    struct
    {
      volatile uint32_t mfc : 16;
      volatile uint32_t obmfc : 1;
      volatile uint32_t ofc : 11;
      volatile uint32_t obfoc : 1;
      volatile uint32_t reserved1 : 3;
    } mfbocnt_bit;
  };




  volatile uint32_t reserved1[9];




  union
  {
    volatile uint32_t ctd;
    struct
    {
      volatile uint32_t htdap : 32;
    } ctd_bit;
  };




  union
  {
    volatile uint32_t crd;
    struct
    {
      volatile uint32_t hrdap : 32;
    } crd_bit;
  };




  union
  {
    volatile uint32_t ctbaddr;
    struct
    {
      volatile uint32_t htbap : 32;
    } ctbaddr_bit;
  };




  union
  {
    volatile uint32_t crbaddr;
    struct
    {
      volatile uint32_t hrbap : 32;
    } crbaddr_bit;
  };
} emac_dma_type;
# 1567 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_emac.h"
void emac_reset(void);
void emac_clock_range_set(void);
void emac_dma_software_reset_set(void);
flag_status emac_dma_software_reset_get(void);
void emac_start(void);
void emac_stop(void);
error_status emac_phy_register_write(uint8_t address, uint8_t reg, uint16_t data);
error_status emac_phy_register_read(uint8_t address, uint8_t reg, uint16_t *data);
void emac_control_para_init(emac_control_config_type *control_para);
void emac_control_config(emac_control_config_type *control_struct);
void emac_receiver_enable(confirm_state new_state);
void emac_trasmitter_enable(confirm_state new_state);
void emac_deferral_check_set(confirm_state new_state);
void emac_backoff_limit_set(emac_bol_type slot_time);
void emac_auto_pad_crc_stripping_set(confirm_state new_state);
void emac_retry_disable(confirm_state new_state);
void emac_ipv4_checksum_offload_set(confirm_state new_state);
void emac_loopback_mode_enable(confirm_state new_state);
void emac_receive_own_disable(confirm_state new_state);
void emac_carrier_sense_disable(confirm_state new_state);
void emac_interframe_gap_set(emac_intergrame_gap_type number);
void emac_jabber_disable(confirm_state new_state);
void emac_watchdog_disable(confirm_state new_state);
void emac_fast_speed_set(emac_speed_type speed);
void emac_duplex_mode_set(emac_duplex_type duplex_mode);
void emac_promiscuous_mode_set(confirm_state new_state);
void emac_hash_unicast_set(confirm_state new_state);
void emac_hash_multicast_set(confirm_state new_state);
void emac_dstaddr_inverse_filter_set(confirm_state new_state);
void emac_pass_all_multicasting_set(confirm_state new_state);
void emac_broadcast_frames_disable(confirm_state new_state);
void emac_pass_control_frames_set(emac_control_frames_filter_type condition);
void emac_srcaddr_inverse_filter_set(confirm_state new_state);
void emac_srcaddr_filter_set(confirm_state new_state);
void emac_hash_perfect_filter_set(confirm_state new_state);
void emac_receive_all_set(confirm_state new_state);
void emac_hash_table_high32bits_set(uint32_t high32bits);
void emac_hash_table_low32bits_set(uint32_t low32bits);
flag_status emac_mii_busy_get(void);
void emac_mii_write(confirm_state new_state);
void emac_fcb_bpa_set(confirm_state new_state);
void emac_transmit_flow_control_enable(confirm_state new_state);
void emac_receive_flow_control_enable(confirm_state new_state);
void emac_unicast_pause_frame_detect(confirm_state new_state);
void emac_pause_low_threshold_set(emac_pause_slot_threshold_type pasue_threshold);
void emac_zero_quanta_pause_disable(confirm_state new_state);
void emac_pause_time_set(uint16_t pause_time);
void emac_vlan_tag_identifier_set(uint16_t identifier);
void emac_vlan_tag_comparison_set(confirm_state new_state);
void emac_wakeup_frame_set(uint32_t value);
uint32_t emac_wakeup_frame_get(void);
void emac_power_down_set(confirm_state new_state);
void emac_magic_packet_enable(confirm_state new_state);
void emac_wakeup_frame_enable(confirm_state new_state);
flag_status emac_received_magic_packet_get(void);
flag_status emac_received_wakeup_frame_get(void);
void emac_global_unicast_set(confirm_state new_state);
void emac_wakeup_frame_filter_reset(confirm_state new_state);
flag_status emac_interrupt_status_read(uint32_t flag);
void emac_interrupt_mask_set(emac_interrupt_mask_type mask_type, confirm_state new_state);
void emac_local_address_set(uint8_t *address);
void emac_address_filter_set(emac_address_type mac, emac_address_filter_type filter, emac_address_mask_type mask_bit, confirm_state new_state);
uint32_t emac_received_packet_size_get(void);
uint32_t emac_dmarxdesc_frame_length_get(emac_dma_desc_type *dma_rx_desc);
void emac_dma_descriptor_list_address_set(emac_dma_tx_rx_type transfer_type, emac_dma_desc_type *dma_desc_tab, uint8_t *buff, uint32_t buffer_count);
uint32_t emac_dma_descriptor_list_address_get(emac_dma_tx_rx_type transfer_type);
void emac_dma_rx_desc_interrupt_config(emac_dma_desc_type *dma_rx_desc, confirm_state new_state);
void emac_dma_para_init(emac_dma_config_type *control_para);
void emac_dma_config(emac_dma_config_type *control_para);
void emac_dma_arbitation_set(emac_dma_rx_tx_ratio_type ratio, confirm_state new_state);
void emac_dma_descriptor_skip_length_set(uint8_t length);
void emac_dma_separate_pbl_set(emac_dma_pbl_type tx_length, emac_dma_pbl_type rx_length, confirm_state new_state);
void emac_dma_eight_pbl_mode_set(confirm_state new_state);
void emac_dma_address_aligned_beats_set(confirm_state new_state);
void emac_dma_poll_demand_set(emac_dma_tx_rx_type transfer_type, uint32_t value);
uint32_t emac_dma_poll_demand_get(emac_dma_tx_rx_type transfer_type);
emac_dma_receive_process_status_type emac_dma_receive_status_get(void);
emac_dma_transmit_process_status_type emac_dma_transmit_status_get(void);
void emac_dma_operations_set(emac_dma_operations_type ops, confirm_state new_state);
void emac_dma_receive_threshold_set(emac_dma_receive_threshold_type value);
void emac_dma_transmit_threshold_set(emac_dma_transmit_threshold_type value);
void emac_dma_interrupt_enable(emac_dma_interrupt_type it, confirm_state new_state);
uint16_t emac_dma_controller_missing_frame_get(void);
uint8_t emac_dma_missing_overflow_bit_get(void);
uint16_t emac_dma_application_missing_frame_get(void);
uint8_t emac_dma_fifo_overflow_bit_get(void);
uint32_t emac_dma_tansfer_address_get(emac_dma_transfer_address_type transfer_type);
void emac_mmc_counter_reset(void);
void emac_mmc_rollover_stop(confirm_state new_state);
void emac_mmc_reset_on_read_enable(confirm_state new_state);
void emac_mmc_counter_freeze(confirm_state new_state);
flag_status emac_mmc_received_status_get(uint32_t flag);
flag_status emac_mmc_transmit_status_get(uint32_t flag);
void emac_mmc_received_interrupt_mask_set(uint32_t flag, confirm_state new_state);
void emac_mmc_transmit_interrupt_mask_set(uint32_t flag, confirm_state new_state);
uint32_t emac_mmc_transmit_good_frames_get(uint32_t flag);
uint32_t emac_mmc_received_error_frames_get(uint32_t flag);
void emac_ptp_timestamp_enable(confirm_state new_state);
void emac_ptp_timestamp_fine_update_enable(confirm_state new_state);
void emac_ptp_timestamp_system_time_init(confirm_state new_state);
void emac_ptp_timestamp_system_time_update(confirm_state new_state);
void emac_ptp_interrupt_trigger_enable(confirm_state new_state);
void emac_ptp_addend_register_update(confirm_state new_state);
void emac_ptp_snapshot_received_frames_enable(confirm_state new_state);
void emac_ptp_subsecond_rollover_enable(confirm_state new_state);
void emac_ptp_psv2_enable(confirm_state new_state);
void emac_ptp_snapshot_emac_frames_enable(confirm_state new_state);
void emac_ptp_snapshot_ipv6_frames_enable(confirm_state new_state);
void emac_ptp_snapshot_ipv4_frames_enable(confirm_state new_state);
void emac_ptp_snapshot_event_message_enable(confirm_state new_state);
void emac_ptp_snapshot_master_event_enable(confirm_state new_state);
void emac_ptp_clock_node_set(emac_ptp_clock_node_type node);
void emac_ptp_mac_address_filter_enable(confirm_state new_state);
void emac_ptp_subsecond_increment_set(uint8_t value);
uint32_t emac_ptp_system_second_get(void);
uint32_t emac_ptp_system_subsecond_get(void);
confirm_state emac_ptp_system_time_sign_get(void);
void emac_ptp_system_second_set(uint32_t second);
void emac_ptp_system_subsecond_set(uint32_t subsecond);
void emac_ptp_system_time_sign_set(confirm_state sign);
void emac_ptp_timestamp_addend_set(uint32_t value);
void emac_ptp_target_second_set(uint32_t value);
void emac_ptp_target_nanosecond_set(uint32_t value);
confirm_state emac_ptp_timestamp_status_get(emac_ptp_timestamp_status_type status);
void emac_ptp_pps_frequency_set(emac_ptp_pps_control_type freq);
flag_status emac_dma_flag_get(uint32_t dma_flag);
void emac_dma_flag_clear(uint32_t dma_flag);
# 160 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_dvp.h" 1
# 99 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_dvp.h"
typedef enum
{
  DVP_CAP_FUNC_MODE_CONTINUOUS = 0x00,
  DVP_CAP_FUNC_MODE_SINGLE = 0x01
} dvp_cfm_type;




typedef enum
{
  DVP_SYNC_MODE_HARDWARE = 0x00,
  DVP_SYNC_MODE_EMBEDDED = 0x01
} dvp_sm_type;




typedef enum
{
  DVP_CLK_POLARITY_RISING = 0x00,
  DVP_CLK_POLARITY_FALLING = 0x01
} dvp_ckp_type;




typedef enum
{
  DVP_HSYNC_POLARITY_HIGH = 0x00,
  DVP_HSYNC_POLARITY_LOW = 0x01
} dvp_hsp_type;




typedef enum
{
  DVP_VSYNC_POLARITY_LOW = 0x00,
  DVP_VSYNC_POLARITY_HIGH = 0x01
} dvp_vsp_type;




typedef enum
{
  DVP_BFRC_ALL = 0x00,
  DVP_BFRC_HALF = 0x01,
  DVP_BFRC_QUARTER = 0x02
} dvp_bfrc_type;




typedef enum
{
  DVP_PIXEL_DATA_LENGTH_8 = 0x00,
  DVP_PIXEL_DATA_LENGTH_10 = 0x01,
  DVP_PIXEL_DATA_LENGTH_12 = 0x02,
  DVP_PIXEL_DATA_LENGTH_14 = 0x03
} dvp_pdl_type;




typedef enum
{
  DVP_PCDC_ALL = 0x00,
  DVP_PCDC_ONE_IN_TWO = 0x01,
  DVP_PCDC_ONE_IN_FOUR = 0x02,
  DVP_PCDC_TWO_IN_FOUR = 0x03
} dvp_pcdc_type;




typedef enum
{
  DVP_PCDS_CAP_FIRST = 0x00,
  DVP_PCDS_DROP_FIRST = 0x01
} dvp_pcds_type;




typedef enum
{
  DVP_LCDC_ALL = 0x00,
  DVP_LCDC_ONE_IN_TWO = 0x01
} dvp_lcdc_type;




typedef enum
{
  DVP_LCDS_CAP_FIRST = 0x00,
  DVP_LCDS_DROP_FIRST = 0x01
} dvp_lcds_type;




typedef enum
{
  DVP_STATUS_HSYN = 0x00,
  DVP_STATUS_VSYN = 0x01,
  DVP_STATUS_OFNE = 0x02
} dvp_status_basic_type;




typedef enum
{
  DVP_PCDES_CAP_FIRST = 0x00,
  DVP_PCDES_DROP_FIRST = 0x01
} dvp_pcdes_type;




typedef enum
{
  DVP_EFDF_BYPASS = 0x00,
  DVP_EFDF_YUV422_UYVY = 0x04,
  DVP_EFDF_YUV422_YUYV = 0x05,
  DVP_EFDF_RGB565_555 = 0x06,
  DVP_EFDF_Y8 = 0x07
} dvp_efdf_type;




typedef enum
{
  DVP_IDUS_MSB = 0x00,
  DVP_IDUS_LSB = 0x01
} dvp_idus_type;




typedef enum
{
  DVP_DMABT_SINGLE = 0x00,
  DVP_DMABT_BURST = 0x01
} dvp_dmabt_type;




typedef enum
{
  DVP_HSEID_LINE_END = 0x00,
  DVP_HSEID_LINE_START = 0x01
} dvp_hseid_type;




typedef enum
{
  DVP_VSEID_FRAME_END = 0x00,
  DVP_VSEID_FRMAE_START = 0x01
} dvp_vseid_type;



typedef enum
{
  DVP_IDUN_0 = 0x00,
  DVP_IDUN_2 = 0x01,
  DVP_IDUN_4 = 0x02,
  DVP_IDUN_6 = 0x03
} dvp_idun_type;

typedef struct
{



  union
  {
    volatile uint32_t ctrl;
    struct
    {
      volatile uint32_t cap : 1;
      volatile uint32_t cfm : 1;
      volatile uint32_t crp : 1;
      volatile uint32_t jpeg : 1;
      volatile uint32_t sm : 1;
      volatile uint32_t ckp : 1;
      volatile uint32_t hsp : 1;
      volatile uint32_t vsp : 1;
      volatile uint32_t bfrc : 2;
      volatile uint32_t pdl : 2;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t ena : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t pcdc : 2;
      volatile uint32_t pcds : 1;
      volatile uint32_t lcdc : 1;
      volatile uint32_t lcds : 1;
      volatile uint32_t : 11;
    } ctrl_bit;
  };




  union
  {
    volatile uint32_t sts;
    struct
    {
      volatile uint32_t hsyn : 1;
      volatile uint32_t vsyn : 1;
      volatile uint32_t ofne : 1;
      volatile uint32_t reserved1 : 29;
    } sts_bit;
  };




  union
  {
    volatile uint32_t ests;
    struct
    {
      volatile uint32_t cfdes : 1;
      volatile uint32_t ovres : 1;
      volatile uint32_t esees : 1;
      volatile uint32_t vses : 1;
      volatile uint32_t hses : 1;
      volatile uint32_t reserved1 : 27;
    } ests_bit;
  };




  union
  {
    volatile uint32_t ier;
    struct
    {
      volatile uint32_t cfdie : 1;
      volatile uint32_t ovrie : 1;
      volatile uint32_t eseie : 1;
      volatile uint32_t vsie : 1;
      volatile uint32_t hsie : 1;
      volatile uint32_t reserved1 : 27;
    } ier_bit;
  };




  union
  {
    volatile uint32_t ists;
    struct
    {
      volatile uint32_t cfdis : 1;
      volatile uint32_t ovris : 1;
      volatile uint32_t eseis : 1;
      volatile uint32_t vsis : 1;
      volatile uint32_t hsis : 1;
      volatile uint32_t reserved1 : 27;
    } ists_bit;
  };




  union
  {
    volatile uint32_t iclr;
    struct
    {
      volatile uint32_t cfdic : 1;
      volatile uint32_t ovric : 1;
      volatile uint32_t eseic : 1;
      volatile uint32_t vsic : 1;
      volatile uint32_t hsic : 1;
      volatile uint32_t reserved1 : 27;
    } iclr_bit;
  };




  union
  {
    volatile uint32_t scr;
    struct
    {
      volatile uint32_t fmsc : 8;
      volatile uint32_t lnsc : 8;
      volatile uint32_t lnec : 8;
      volatile uint32_t fmec : 8;
    } scr_bit;
  };




  union
  {
    volatile uint32_t sur;
    struct
    {
      volatile uint32_t fmsu : 8;
      volatile uint32_t lnsu : 8;
      volatile uint32_t lneu : 8;
      volatile uint32_t fmeu : 8;
    } sur_bit;
  };




  union
  {
    volatile uint32_t cwst;
    struct
    {
      volatile uint32_t chstr : 14;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t cvstr : 13;
      volatile uint32_t reserved2 : 3;
    } cwst_bit;
  };




  union
  {
    volatile uint32_t cwsz;
    struct
    {
      volatile uint32_t chnum : 14;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t cvnum : 14;
      volatile uint32_t reserved2 : 2;
    } cwsz_bit;
  };




  union
  {
    volatile uint32_t dt;
    struct
    {
      volatile uint32_t dr0 : 8;
      volatile uint32_t dr1 : 8;
      volatile uint32_t dr2 : 8;
      volatile uint32_t dr3 : 8;
    } dt_bit;
  };




  volatile uint32_t reserved1[5];




  union
  {
    volatile uint32_t actrl;
    struct
    {
      volatile uint32_t eisre : 1;
      volatile uint32_t efrce : 1;
      volatile uint32_t mibe : 1;
      volatile uint32_t pcdes : 1;
      volatile uint32_t efdf : 3;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t idun : 2;
      volatile uint32_t idus : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t dmabt : 1;
      volatile uint32_t reserved3 : 1;
      volatile uint32_t reserved4 : 1;
      volatile uint32_t reserved5 : 1;
      volatile uint32_t hseid : 1;
      volatile uint32_t vseid : 1;
      volatile uint32_t reserved6 : 1;
      volatile uint32_t reserved7 : 2;
      volatile uint32_t reserved8 : 11;
    } actrl_bit;
  };




  volatile uint32_t reserved2;




  union
  {
    volatile uint32_t hscf;
    struct
    {
      volatile uint32_t hsrss : 13;
      volatile uint32_t reserved1 : 3;
      volatile uint32_t hsrts : 13;
      volatile uint32_t reserved2 : 3;
    } hscf_bit;
  };




  union
  {
    volatile uint32_t vscf;
    struct
    {
      volatile uint32_t vsrss : 13;
      volatile uint32_t reserved1 : 3;
      volatile uint32_t vsrts : 13;
      volatile uint32_t reserved2 : 3;
    } vscf_bit;
  };




  union
  {
    volatile uint32_t frf;
    struct
    {
      volatile uint32_t efrcsf : 5;
      volatile uint32_t reserved1 : 3;
      volatile uint32_t efrctf : 5;
      volatile uint32_t reserved2 : 19;
    } frf_bit;
  };




  union
  {
    volatile uint32_t bth;
    struct
    {
      volatile uint32_t mibthd : 8;
      volatile uint32_t reserved1 : 24;
    } bth_bit;
  };

} dvp_type;
# 575 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_dvp.h"
void dvp_reset(void);
void dvp_capture_enable(confirm_state new_state);
void dvp_capture_enable(confirm_state new_state);
void dvp_capture_mode_set(dvp_cfm_type cap_mode);
void dvp_window_crop_enable(confirm_state new_state);
void dvp_window_crop_set(uint16_t crop_x, uint16_t crop_y, uint16_t crop_w, uint16_t crop_h, uint8_t bytes);
void dvp_jpeg_enable(confirm_state new_state);
void dvp_sync_mode_set(dvp_sm_type sync_mode);
void dvp_sync_code_set(uint8_t fmsc, uint8_t fmec, uint8_t lnsc, uint8_t lnec);
void dvp_sync_unmask_set(uint8_t fmsu, uint8_t fmeu, uint8_t lnsu, uint8_t lneu);
void dvp_pclk_polarity_set(dvp_ckp_type eage);
void dvp_hsync_polarity_set(dvp_hsp_type hsync_pol);
void dvp_vsync_polarity_set(dvp_vsp_type vsync_pol);
void dvp_basic_frame_rate_control_set(dvp_bfrc_type dvp_bfrc);
void dvp_pixel_data_length_set(dvp_pdl_type dvp_pdl);
void dvp_enable(confirm_state new_state);
void dvp_zoomout_select(dvp_pcdes_type dvp_pcdes);
void dvp_zoomout_set(dvp_pcdc_type dvp_pcdc, dvp_pcds_type dvp_pcds, dvp_lcdc_type dvp_lcdc, dvp_lcds_type dvp_lcds);
flag_status dvp_basic_status_get(dvp_status_basic_type dvp_status_basic);
void dvp_interrupt_enable(uint32_t dvp_int, confirm_state new_state);
flag_status dvp_flag_get(uint32_t flag);
void dvp_flag_clear(uint32_t flag);
void dvp_enhanced_scaling_resize_enable(confirm_state new_state);
void dvp_enhanced_scaling_resize_set(uint16_t src_w, uint16_t des_w, uint16_t src_h, uint16_t des_h);
void dvp_enhanced_framerate_set(uint16_t efrcsf, uint16_t efrctf, confirm_state new_state);
void dvp_monochrome_image_binarization_set(uint8_t mibthd, confirm_state new_state);
void dvp_enhanced_data_format_set(dvp_efdf_type dvp_efdf);
void dvp_input_data_unused_set(dvp_idus_type dvp_idus, dvp_idun_type dvp_idun);
void dvp_dma_burst_set(dvp_dmabt_type dvp_dmabt);
void dvp_sync_event_interrupt_set(dvp_hseid_type dvp_hseid, dvp_vseid_type dvp_vseid);
# 163 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2


# 1 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_usb.h" 1
# 250 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_usb.h"
typedef enum
{
  DCFG_PERFRINT_80 = 0x00,
  DCFG_PERFRINT_85 = 0x01,
  DCFG_PERFRINT_90 = 0x02,
  DCFG_PERFRINT_95 = 0x03
} dcfg_perfrint_type;
# 334 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_usb.h"
typedef enum
{
  OTG_DEVICE_MODE,
  OTG_HOST_MODE,
  OTG_DRD_MODE
} otg_mode_type;




typedef enum
{
  EPT_CONTROL_TYPE = 0x00,
  EPT_ISO_TYPE = 0x01,
  EPT_BULK_TYPE = 0x02,
  EPT_INT_TYPE = 0x03
} endpoint_trans_type;




typedef enum
{
  USB_EPT0 = 0x00,
  USB_EPT1 = 0x01,
  USB_EPT2 = 0x02,
  USB_EPT3 = 0x03,
  USB_EPT4 = 0x04,
  USB_EPT5 = 0x05,
  USB_EPT6 = 0x06,
  USB_EPT7 = 0x07
} usb_endpoint_number_type;
# 383 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_usb.h"
typedef enum
{
  EPT_DIR_IN = 0x00,
  EPT_DIR_OUT = 0x01
} endpoint_dir_type;




typedef enum
{
  USB_OTG1_ID,
  USB_OTG2_ID
} otg_id_type;




typedef enum
{
  USB_CLK_HICK,
  USB_CLK_HEXT
}usb_clk48_s;
# 420 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_usb.h"
typedef struct
{
  uint8_t eptn;
  uint8_t ept_address;
  uint8_t inout;
  uint8_t trans_type;

  uint16_t tx_addr;
  uint16_t rx_addr;
  uint32_t maxpacket;
  uint8_t is_double_buffer;
  uint8_t stall;
  uint32_t status;


  uint8_t *trans_buf;
  uint32_t total_len;
  uint32_t trans_len;

  uint32_t last_len;
  uint32_t rem0_len;
  uint32_t ept0_slen;
} usb_ept_info;





typedef struct
{
  uint8_t ch_num;
  uint8_t address;
  uint8_t dir;
  uint8_t ept_num;
  uint8_t ept_type;
  uint32_t maxpacket;
  uint8_t data_pid;
  uint8_t speed;
  uint8_t stall;
  uint32_t status;
  uint32_t state;
  uint32_t urb_sts;

  uint8_t toggle_in;
  uint8_t toggle_out;


  uint8_t *trans_buf;
  uint32_t trans_len;
  uint32_t trans_count;
} usb_hch_type;


typedef struct
{



  union
  {
    volatile uint32_t gotgctrl;
    struct
    {
      volatile uint32_t reserved1 : 16;
      volatile uint32_t cidsts : 1;
      volatile uint32_t reserved2 : 4;
      volatile uint32_t curmod : 1;
      volatile uint32_t reserved3 : 10;
    } gotgctrl_bit;
  };




  union
  {
    volatile uint32_t gotgint;
    struct
    {
      volatile uint32_t reserved1 : 2;
      volatile uint32_t sesenddet : 1;
      volatile uint32_t reserved2 : 29;

    } gotgint_bit;
  };




  union
  {
    volatile uint32_t gahbcfg;
    struct
    {
      volatile uint32_t glbintmsk : 1;
      volatile uint32_t reserved1 : 6;
      volatile uint32_t nptxfemplvl : 1;
      volatile uint32_t ptxfemplvl : 1;
      volatile uint32_t reserved2 : 23;
    } gahbcfg_bit;
  };




  union
  {
    volatile uint32_t gusbcfg;
    struct
    {
      volatile uint32_t toutcal : 3;
      volatile uint32_t reserved1 : 7;
      volatile uint32_t usbtrdtim : 4;
      volatile uint32_t reserved2 : 15;
      volatile uint32_t fhstmode : 1;
      volatile uint32_t fdevmode : 1;
      volatile uint32_t cotxpkt : 1;
    } gusbcfg_bit;
  };




  union
  {
    volatile uint32_t grstctl;
    struct
    {
      volatile uint32_t csftrst : 1;
      volatile uint32_t piusftrst : 1;
      volatile uint32_t frmcntrst : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t rxfflsh : 1;
      volatile uint32_t txfflsh : 1;
      volatile uint32_t txfnum : 5;
      volatile uint32_t reserved2 : 20;
      volatile uint32_t ahbidle : 1;
    } grstctl_bit;
  };




  union
  {
    volatile uint32_t gintsts;
    struct
    {
      volatile uint32_t curmode : 1;
      volatile uint32_t modemis : 1;
      volatile uint32_t otgint : 1;
      volatile uint32_t sof : 1;
      volatile uint32_t rxflvl : 1;
      volatile uint32_t nptxfemp : 1;
      volatile uint32_t ginnakeff : 1;
      volatile uint32_t goutnakeff : 1;
      volatile uint32_t reserved1 : 2;
      volatile uint32_t erlysusp : 1;
      volatile uint32_t usbsusp : 1;
      volatile uint32_t usbrst : 1;
      volatile uint32_t enumdone : 1;
      volatile uint32_t isooutdrop : 1;
      volatile uint32_t eopf : 1;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t ieptint : 1;
      volatile uint32_t oeptint : 1;
      volatile uint32_t incompisoin : 1;
      volatile uint32_t incompip_incompisoout : 1;
      volatile uint32_t reserved3 : 2;
      volatile uint32_t prtint : 1;
      volatile uint32_t hchint : 1;
      volatile uint32_t ptxfemp : 1;
      volatile uint32_t reserved4 : 1;
      volatile uint32_t conidschg : 1;
      volatile uint32_t disconint : 1;
      volatile uint32_t reserved5 : 1;
      volatile uint32_t wkupint : 1;
    } gintsts_bit;
  };




  union
  {
    volatile uint32_t gintmsk;
    struct
    {
      volatile uint32_t reserved1 : 1;
      volatile uint32_t modemismsk : 1;
      volatile uint32_t otgintmsk : 1;
      volatile uint32_t sofmsk : 1;
      volatile uint32_t rxflvlmsk : 1;
      volatile uint32_t nptxfempmsk : 1;
      volatile uint32_t ginnakeffmsk : 1;
      volatile uint32_t goutnakeffmsk : 1;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t erlysuspmsk : 1;
      volatile uint32_t usbsuspmsk : 1;
      volatile uint32_t usbrstmsk : 1;
      volatile uint32_t enumdonemsk : 1;
      volatile uint32_t isooutdropmsk : 1;
      volatile uint32_t eopfmsk : 1;
      volatile uint32_t reserved3 : 2;
      volatile uint32_t ieptintmsk : 1;
      volatile uint32_t oeptintmsk : 1;
      volatile uint32_t incompisoinmsk : 1;
      volatile uint32_t incompip_incompisooutmsk : 1;
      volatile uint32_t reserved4 : 2;
      volatile uint32_t prtintmsk : 1;
      volatile uint32_t hchintmsk : 1;
      volatile uint32_t ptxfempmsk : 1;
      volatile uint32_t reserved5 : 1;
      volatile uint32_t conidschgmsk : 1;
      volatile uint32_t disconintmsk : 1;
      volatile uint32_t reserved6 : 1;
      volatile uint32_t wkupintmsk : 1;
    } gintmsk_bit;
  };




  union
  {
    volatile uint32_t grxstsr;
    struct
    {
      volatile uint32_t eptnum : 4;
      volatile uint32_t bcnt : 11;
      volatile uint32_t dpid : 2;
      volatile uint32_t pktsts : 4;
      volatile uint32_t fn : 4;
      volatile uint32_t reserved1 : 7;
    } grxstsr_bit;
  };




  union
  {
    volatile uint32_t grxstsp;
    struct
    {
      volatile uint32_t chnum : 4;
      volatile uint32_t bcnt : 11;
      volatile uint32_t dpid : 2;
      volatile uint32_t pktsts : 4;
      volatile uint32_t reserved1 : 11;
    } grxstsp_bit;
  };




  union
  {
    volatile uint32_t grxfsiz;
    struct
    {
      volatile uint32_t rxfdep : 16;
      volatile uint32_t reserved1 : 16;
    } grxfsiz_bit;
  };




  union
  {
    volatile uint32_t gnptxfsiz_ept0tx;
    struct
    {
      volatile uint32_t nptxfstaddr : 16;
      volatile uint32_t nptxfdep : 16;
    } gnptxfsiz_ept0tx_bit;
  };




  union
  {
    volatile uint32_t gnptxsts;
    struct
    {
      volatile uint32_t nptxfspcavail : 16;
      volatile uint32_t nptxqspcavail : 8;
      volatile uint32_t nptxqtop : 7;
    } gnptxsts_bit;
  };

  volatile uint32_t reserved2[2];




  union
  {
    volatile uint32_t gccfg;
    struct
    {
      volatile uint32_t reserved1 : 16;
      volatile uint32_t pwrdown : 1;
      volatile uint32_t lp_mode : 1;
      volatile uint32_t reserved2 : 2;
      volatile uint32_t sofouten : 1;
      volatile uint32_t vbusig : 1;
      volatile uint32_t reserved3 : 10;
    } gccfg_bit;
  };




  union
  {
    volatile uint32_t guid;
    struct
    {
      volatile uint32_t userid : 32;
    } guid_bit;
  };

  volatile uint32_t reserved3[48];




  union
  {
    volatile uint32_t hptxfsiz;
    struct
    {
      volatile uint32_t ptxfstaddr : 16;
      volatile uint32_t ptxfsize : 16;
    } hptxfsiz_bit;
  };




  union
  {
    volatile uint32_t dieptxfn[7];
    struct
    {
      volatile uint32_t ineptxfstaddr : 16;
      volatile uint32_t ineptxfdep : 16;
    } dieptxfn_bit[7];
  };
} otg_global_type;


typedef struct
{



  union
  {
    volatile uint32_t hcfg;
    struct
    {
      volatile uint32_t fslspclksel : 2;
      volatile uint32_t fslssupp : 1;
      volatile uint32_t reserved1 : 29;
    } hcfg_bit;
  };




  union
  {
    volatile uint32_t hfir;
    struct
    {
      volatile uint32_t frint : 16;
      volatile uint32_t reserved1 : 16;
    } hfir_bit;
  };




  union
  {
    volatile uint32_t hfnum;
    struct
    {
      volatile uint32_t frnum : 16;
      volatile uint32_t ftrem : 16;
    } hfnum_bit;
  };

  volatile uint32_t reserved1;




  union
  {
    volatile uint32_t hptxsts;
    struct
    {
      volatile uint32_t ptxfspcavil : 16;
      volatile uint32_t ptxqspcavil : 8;
      volatile uint32_t ptxqtop : 8;
    } hptxsts_bit;
  };




  union
  {
    volatile uint32_t haint;
    struct
    {
      volatile uint32_t haint : 16;
      volatile uint32_t reserved1 : 16;
    } haint_bit;
  };




  union
  {
    volatile uint32_t haintmsk;
    struct
    {
      volatile uint32_t haintmsk : 16;
      volatile uint32_t reserved1 : 16;
    } haintmsk_bit;
  };

  volatile uint32_t reserved2[9];




  union
  {
    volatile uint32_t hprt;
    struct
    {
      volatile uint32_t prtconsts : 1;
      volatile uint32_t prtcondet : 1;
      volatile uint32_t prtena : 1;
      volatile uint32_t prtenchng : 1;
      volatile uint32_t prtovrcact : 1;
      volatile uint32_t prtovrcchng : 1;
      volatile uint32_t prtres : 1;
      volatile uint32_t prtsusp : 1;
      volatile uint32_t prtrst : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t prtlnsts : 2;
      volatile uint32_t prtpwr : 1;
      volatile uint32_t prttsctl : 4;
      volatile uint32_t prtspd : 2;
      volatile uint32_t reserved2 : 13;

    } hprt_bit;
  };
} otg_host_type;

typedef struct
{



  union
  {
    volatile uint32_t hcchar;
    struct
    {
      volatile uint32_t mps : 11;
      volatile uint32_t eptnum : 4;
      volatile uint32_t eptdir : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t lspddev : 1;
      volatile uint32_t eptype : 2;
      volatile uint32_t mc : 2;
      volatile uint32_t devaddr : 7;
      volatile uint32_t oddfrm : 1;
      volatile uint32_t chdis : 1;
      volatile uint32_t chena : 1;
    } hcchar_bit;
  };




  union
  {
    volatile uint32_t hcsplt;
    struct
    {
      volatile uint32_t prtaddr : 7;
      volatile uint32_t hubaddr : 7;
      volatile uint32_t xactpos : 2;
      volatile uint32_t compsplt : 1;
      volatile uint32_t reserved1 : 14;
      volatile uint32_t spltena : 1;
    } hcsplt_bit;
  };




  union
  {
    volatile uint32_t hcint;
    struct
    {
      volatile uint32_t xferc : 1;
      volatile uint32_t chhltd : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t stall : 1;
      volatile uint32_t nak : 1;
      volatile uint32_t ack : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t xacterr : 1;
      volatile uint32_t bblerr : 1;
      volatile uint32_t frmovrun : 1;
      volatile uint32_t dtglerr : 1;
      volatile uint32_t reserved3 : 21;
    } hcint_bit;
  };




  union
  {
    volatile uint32_t hcintmsk;
    struct
    {
      volatile uint32_t xfercmsk : 1;
      volatile uint32_t chhltdmsk : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t stallmsk : 1;
      volatile uint32_t nakmsk : 1;
      volatile uint32_t ackmsk : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t xacterrmsk : 1;
      volatile uint32_t bblerrmsk : 1;
      volatile uint32_t frmovrunmsk : 1;
      volatile uint32_t dtglerrmsk : 1;
      volatile uint32_t reserved3 : 21;
    } hcintmsk_bit;
  };




  union
  {
    volatile uint32_t hctsiz;
    struct
    {
      volatile uint32_t xfersize : 19;
      volatile uint32_t pktcnt : 10;
      volatile uint32_t pid : 2;
      volatile uint32_t reserved1 : 1;
    } hctsiz_bit;
  };
  volatile uint32_t reserved3[3];

}otg_hchannel_type;


typedef struct
{



  union
  {
    volatile uint32_t dcfg;
    struct
    {
      volatile uint32_t devspd : 2;
      volatile uint32_t nzstsouthshk : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t devaddr : 7;
      volatile uint32_t perfrint : 2;
      volatile uint32_t reserved2 : 19;
    } dcfg_bit;
  };




  union
  {
    volatile uint32_t dctl;
    struct
    {
      volatile uint32_t rwkupsig : 1;
      volatile uint32_t sftdiscon : 1;
      volatile uint32_t gnpinnaksts : 1;
      volatile uint32_t goutnaksts : 1;
      volatile uint32_t tstctl : 3;
      volatile uint32_t sgnpinak : 1;
      volatile uint32_t cgnpinak : 1;
      volatile uint32_t sgoutnak : 1;
      volatile uint32_t cgoutnak : 1;
      volatile uint32_t pwroprgdne : 1;
      volatile uint32_t reserved1 : 20;
    } dctl_bit;
  };




  union
  {
    volatile uint32_t dsts;
    struct
    {
      volatile uint32_t suspsts : 1;
      volatile uint32_t enumspd : 2;
      volatile uint32_t eticerr : 1;
      volatile uint32_t reserved1 : 4;
      volatile uint32_t soffn : 14;
      volatile uint32_t reserved2 : 10;
    } dsts_bit;
  };

   volatile uint32_t reserved1;



  union
  {
    volatile uint32_t diepmsk;
    struct
    {
      volatile uint32_t xfercmsk : 1;
      volatile uint32_t eptdismsk : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t timeoutmsk : 1;
      volatile uint32_t intkntxfempmsk : 1;
      volatile uint32_t intkneptmismsk : 1;
      volatile uint32_t ineptnakmsk : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t txfifoudrmsk : 1;
      volatile uint32_t bnainmsk : 1;
      volatile uint32_t reserved3 : 22;
    } diepmsk_bit;
  };




  union
  {
    volatile uint32_t doepmsk;
    struct
    {
      volatile uint32_t xfercmsk : 1;
      volatile uint32_t eptdismsk : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t setupmsk : 1;
      volatile uint32_t outtepdmsk : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t b2bsetupmsk : 1;
      volatile uint32_t reserved3 : 1;
      volatile uint32_t outperrmsk : 1;
      volatile uint32_t bnaoutmsk : 1;
      volatile uint32_t reserved4 : 22;
    } doepmsk_bit;
  };




  union
  {
    volatile uint32_t daint;
    struct
    {
      volatile uint32_t ineptint : 16;
      volatile uint32_t outeptint : 16;
    } daint_bit;
  };




  union
  {
    volatile uint32_t daintmsk;
    struct
    {
      volatile uint32_t ineptmsk : 16;
      volatile uint32_t outeptmsk : 16;
    } daintmsk_bit;
  };

  volatile uint32_t reserved2[5];




  union
  {
    volatile uint32_t diepempmsk;
    struct
    {
      volatile uint32_t ineptxfemsk : 16;
      volatile uint32_t reserved1 : 16;
    } diepempmsk_bit;
  };

} otg_device_type;

typedef struct
{



  union
  {
    volatile uint32_t diepctl;
    struct
    {
      volatile uint32_t mps : 11;
      volatile uint32_t reserved1 : 4;
      volatile uint32_t usbacept : 1;
      volatile uint32_t dpid : 1;
      volatile uint32_t naksts : 1;
      volatile uint32_t eptype : 2;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t stall : 1;
      volatile uint32_t txfnum : 4;
      volatile uint32_t cnak : 1;
      volatile uint32_t snak : 1;
      volatile uint32_t setd0pid : 1;
      volatile uint32_t setd1pid : 1;
      volatile uint32_t eptdis : 1;
      volatile uint32_t eptena : 1;
    } diepctl_bit;
  };
  volatile uint32_t reserved1;




  union
  {
    volatile uint32_t diepint;
    struct
    {
      volatile uint32_t xferc : 1;
      volatile uint32_t epdisd : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t timeout : 1;
      volatile uint32_t intkntxfemp : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t ineptnak : 1;
      volatile uint32_t txfemp : 1;
      volatile uint32_t reserved3 : 24;
    } diepint_bit;
  };
  volatile uint32_t reserved2;




  union
  {
    volatile uint32_t dieptsiz;
    struct
    {
      volatile uint32_t xfersize : 19;
      volatile uint32_t pktcnt : 10;
      volatile uint32_t mc : 2;
      volatile uint32_t reserved1 : 1;
    } dieptsiz_bit;
  };

  volatile uint32_t reserved3;




  union
  {
    volatile uint32_t dtxfsts;
    struct
    {
      volatile uint32_t ineptxfsav : 16;
      volatile uint32_t reserved1 : 16;
    } dtxfsts_bit;
  };

} otg_eptin_type;

typedef struct
{



  union
  {
    volatile uint32_t doepctl;
    struct
    {
      volatile uint32_t mps : 11;
      volatile uint32_t reserved1 : 4;
      volatile uint32_t usbacept : 1;
      volatile uint32_t dpid : 1;
      volatile uint32_t naksts : 1;
      volatile uint32_t eptype : 2;
      volatile uint32_t snpm : 1;
      volatile uint32_t stall : 1;
      volatile uint32_t reserved2 : 4;
      volatile uint32_t cnak : 1;
      volatile uint32_t snak : 1;
      volatile uint32_t setd0pid : 1;
      volatile uint32_t setd1pid : 1;
      volatile uint32_t eptdis : 1;
      volatile uint32_t eptena : 1;
    } doepctl_bit;
  };
  volatile uint32_t reserved1;




  union
  {
    volatile uint32_t doepint;
    struct
    {
      volatile uint32_t xferc : 1;
      volatile uint32_t epdisd : 1;
      volatile uint32_t reserved1 : 1;
      volatile uint32_t setup : 1;
      volatile uint32_t outtepd : 1;
      volatile uint32_t reserved2 : 1;
      volatile uint32_t b2pstup : 1;
      volatile uint32_t reserved3 : 25;
    } doepint_bit;
  };
  volatile uint32_t reserved2;




  union
  {
    volatile uint32_t doeptsiz;
    struct
    {
      volatile uint32_t xfersize : 19;
      volatile uint32_t pktcnt : 10;
      volatile uint32_t rxdpid_setupcnt : 2;
      volatile uint32_t reserved1 : 1;
    } doeptsiz_bit;
  };
} otg_eptout_type;

typedef struct
{



  union
  {
    volatile uint32_t pcgcctl;
    struct
    {
      volatile uint32_t stoppclk : 1;
      volatile uint32_t reserved1 : 3;
      volatile uint32_t suspendm : 1;
      volatile uint32_t reserved2 : 27;
    } pcgcctl_bit;
  };
} otg_pcgcctl_type;
# 1340 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_usb.h"
typedef otg_global_type usb_reg_type;






error_status usb_global_reset(otg_global_type *usbx);
void usb_global_init(otg_global_type *usbx);
otg_global_type *usb_global_select_core(uint8_t usb_id);
void usb_flush_tx_fifo(otg_global_type *usbx, uint32_t fifo_num);
void usb_flush_rx_fifo(otg_global_type *usbx);
void usb_global_interrupt_enable(otg_global_type *usbx, uint16_t interrupt, confirm_state new_state);
uint32_t usb_global_get_all_interrupt(otg_global_type *usbx);
void usb_global_clear_interrupt(otg_global_type *usbx, uint32_t flag);
void usb_interrupt_enable(otg_global_type *usbx);
void usb_interrupt_disable(otg_global_type *usbx);
void usb_set_rx_fifo(otg_global_type *usbx, uint16_t size);
void usb_set_tx_fifo(otg_global_type *usbx, uint8_t txfifo, uint16_t size);
void usb_global_set_mode(otg_global_type *usbx, uint32_t mode);
void usb_global_power_on(otg_global_type *usbx);
void usb_write_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uint16_t nbytes);
void usb_read_packet(otg_global_type *usbx, uint8_t *pusr_buf, uint16_t num, uint16_t nbytes);
void usb_stop_phy_clk(otg_global_type *usbx);
void usb_open_phy_clk(otg_global_type *usbx);



void usb_ept_open(otg_global_type *usbx, usb_ept_info *ept_info);
void usb_ept_close(otg_global_type *usbx, usb_ept_info *ept_info);
void usb_ept_stall(otg_global_type *usbx, usb_ept_info *ept_info);
void usb_ept_clear_stall(otg_global_type *usbx, usb_ept_info *ept_info);
uint32_t usb_get_all_out_interrupt(otg_global_type *usbx);
uint32_t usb_get_all_in_interrupt(otg_global_type *usbx);
uint32_t usb_ept_out_interrupt(otg_global_type *usbx, uint32_t eptn);
uint32_t usb_ept_in_interrupt(otg_global_type *usbx, uint32_t eptn);
void usb_ept_out_clear(otg_global_type *usbx, uint32_t eptn, uint32_t flag);
void usb_ept_in_clear(otg_global_type *usbx, uint32_t eptn, uint32_t flag);
void usb_set_address(otg_global_type *usbx, uint8_t address);
void usb_ept0_start(otg_global_type *usbx);
void usb_ept0_setup(otg_global_type *usbx);
void usb_connect(otg_global_type *usbx);
void usb_disconnect(otg_global_type *usbx);
void usb_remote_wkup_set(otg_global_type *usbx);
void usb_remote_wkup_clear(otg_global_type *usbx);
uint8_t usb_suspend_status_get(otg_global_type *usbx);



void usb_port_power_on(otg_global_type *usbx, confirm_state state);
uint32_t usbh_get_frame(otg_global_type *usbx);
void usb_hc_enable(otg_global_type *usbx,
                   uint8_t chn,
                   uint8_t ept_num,
                   uint8_t dev_address,
                   uint8_t type,
                   uint16_t maxpacket,
                   uint8_t speed);
uint32_t usb_hch_read_interrupt(otg_global_type *usbx);
void usb_host_disable(otg_global_type *usbx);
void usb_hch_halt(otg_global_type *usbx, uint8_t chn);
void usbh_fsls_clksel(otg_global_type *usbx, uint8_t clk);
# 166 "../core/AT32F435CGU7/libraries/drivers/inc\\at32f435_437_conf.h" 2
# 28 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c" 2
# 49 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_reset(void)
{


  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->ctrl_bit.hicken = TRUE;


  while(((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->ctrl_bit.hickstbl != SET);


  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->cfg_bit.sclksel = CRM_SCLK_HICK;


  while(((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->cfg_bit.sclksts != CRM_SCLK_HICK);


  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->ctrl &= ~(0x010D0000U);


  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->cfg = 0;


  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->pllcfg = 0x00033002U;


  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->misc1 = 0;


  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->clkint = 0x009F0000U;
}






void crm_lext_bypass(confirm_state new_state)
{
  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->bpdc_bit.lextbyps = new_state;
}






void crm_hext_bypass(confirm_state new_state)
{
  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->ctrl_bit.hextbyps = new_state;
}
# 124 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
flag_status crm_flag_get(uint32_t flag)
{
  flag_status status = RESET;
  if((*(volatile uint32_t *)((((((uint32_t)0x40000000) + 0x20000) + 0x3800) + (flag >> 16))) & (0x1u << (flag & 0x1f))) != (0x1u << (flag & 0x1f)))
  {
    status = RESET;
  }
  else
  {
    status = SET;
  }
  return status;
}






error_status crm_hext_stable_wait(void)
{
  uint32_t stable_cnt = 0;
  error_status status = ERROR;

  while((crm_flag_get((((0x00) << 16) | (17 & 0x1f))) != SET) && (stable_cnt < ((uint16_t)0x3000)))
  {
    stable_cnt ++;
  }

  if(crm_flag_get((((0x00) << 16) | (17 & 0x1f))) != SET)
  {
    status = ERROR;
  }
  else
  {
    status = SUCCESS;
  }

  return status;
}






void crm_hick_clock_trimming_set(uint8_t trim_value)
{
  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->ctrl_bit.hicktrim = trim_value;
}






void crm_hick_clock_calibration_set(uint8_t cali_value)
{

  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->misc1_bit.hickcal_key = 0x5A;


  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->ctrl_bit.hickcal = cali_value;


  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->misc1_bit.hickcal_key = 0x0;
}
# 215 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_periph_clock_enable(crm_periph_clock_type value, confirm_state new_state)
{

  if(TRUE == new_state)
  {
    *(volatile uint32_t *)((((((uint32_t)0x40000000) + 0x20000) + 0x3800) + (value >> 16))) |= (0x1u << (value & 0x1f));
  }

  else
  {
    *(volatile uint32_t *)((((((uint32_t)0x40000000) + 0x20000) + 0x3800) + (value >> 16))) &= ~((0x1u << (value & 0x1f)));
  }
}
# 251 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state)
{

  if(new_state == TRUE)
  {
    *(volatile uint32_t *)((((((uint32_t)0x40000000) + 0x20000) + 0x3800) + (value >> 16))) |= ((0x1u << (value & 0x1f)));
  }

  else
  {
    *(volatile uint32_t *)((((((uint32_t)0x40000000) + 0x20000) + 0x3800) + (value >> 16))) &= ~((0x1u << (value & 0x1f)));
  }
}
# 289 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_periph_lowpower_mode_enable(crm_periph_clock_lowpower_type value, confirm_state new_state)
{

  if(new_state == TRUE)
  {
    *(volatile uint32_t *)((((((uint32_t)0x40000000) + 0x20000) + 0x3800) + (value >> 16))) |= ((0x1u << (value & 0x1f)));
  }

  else
  {
    *(volatile uint32_t *)((((((uint32_t)0x40000000) + 0x20000) + 0x3800) + (value >> 16))) &= ~((0x1u << (value & 0x1f)));
  }
}
# 315 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state)
{
  switch(source)
  {
    case CRM_CLOCK_SOURCE_HICK:
      ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->ctrl_bit.hicken = new_state;
      break;
    case CRM_CLOCK_SOURCE_HEXT:
      ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->ctrl_bit.hexten = new_state;
      break;
    case CRM_CLOCK_SOURCE_PLL:
      ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->ctrl_bit.pllen = new_state;
      break;
    case CRM_CLOCK_SOURCE_LEXT:
      ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->bpdc_bit.lexten = new_state;
      break;
    case CRM_CLOCK_SOURCE_LICK:
      ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->ctrlsts_bit.licken = new_state;
      break;
    default: break;
  }
}
# 359 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_flag_clear(uint32_t flag)
{
  switch(flag)
  {
    case (((0x74) << 16) | (26 & 0x1f)):
    case (((0x74) << 16) | (27 & 0x1f)):
    case (((0x74) << 16) | (28 & 0x1f)):
    case (((0x74) << 16) | (29 & 0x1f)):
    case (((0x74) << 16) | (30 & 0x1f)):
    case (((0x74) << 16) | (31 & 0x1f)):
    case (((0x74) << 16) | (24 & 0x1f)):
      ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->ctrlsts_bit.rstfc = TRUE;
      while(((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->ctrlsts_bit.rstfc == TRUE);
      break;
    case (((0x0C) << 16) | (0 & 0x1f)):
      ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->clkint_bit.lickstblfc = TRUE;
      break;
    case (((0x0C) << 16) | (1 & 0x1f)):
      ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->clkint_bit.lextstblfc = TRUE;
      break;
    case (((0x0C) << 16) | (2 & 0x1f)):
      ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->clkint_bit.hickstblfc = TRUE;
      break;
    case (((0x0C) << 16) | (3 & 0x1f)):
      ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->clkint_bit.hextstblfc = TRUE;
      break;
    case (((0x0C) << 16) | (4 & 0x1f)):
      ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->clkint_bit.pllstblfc = TRUE;
      break;
    case (((0x0C) << 16) | (7 & 0x1f)):
      ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->clkint_bit.cfdfc = TRUE;
      break;
    default:
      break;
  }
}
# 435 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_ertc_clock_select(crm_ertc_clock_type value)
{
  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->cfg_bit.ertcdiv = ((value & 0x1F0) >> 4);
  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->bpdc_bit.ertcsel = (value & 0xF);
}






void crm_ertc_clock_enable(confirm_state new_state)
{
  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->bpdc_bit.ertcen = new_state;
}
# 466 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_ahb_div_set(crm_ahb_div_type value)
{
  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->cfg_bit.ahbdiv = value;
}
# 482 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_apb1_div_set(crm_apb1_div_type value)
{
  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->cfg_bit.apb1div = value;
}
# 498 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_apb2_div_set(crm_apb2_div_type value)
{
  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->cfg_bit.apb2div = value;
}
# 522 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_usb_clock_div_set(crm_usb_div_type value)
{
    ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->misc2_bit.usbdiv = value;
}






void crm_clock_failure_detection_enable(confirm_state new_state)
{
  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->ctrl_bit.cfden = new_state;
}






void crm_battery_powered_domain_reset(confirm_state new_state)
{
  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->bpdc_bit.bpdrst = new_state;
}






void crm_auto_step_mode_enable(confirm_state new_state)
{
  if(new_state == TRUE)
    ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->misc2_bit.auto_step_en = CRM_AUTO_STEP_MODE_ENABLE;
  else
    ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->misc2_bit.auto_step_en = CRM_AUTO_STEP_MODE_DISABLE;
}
# 568 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_hick_divider_select(crm_hick_div_6_type value)
{
  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->misc1_bit.hickdiv = value;
}
# 581 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value)
{
  crm_hick_divider_select(CRM_HICK48_NODIV);
  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->misc1_bit.hick_to_sclk = value;
}
# 595 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_usb_clock_source_select(crm_usb_clock_source_type value)
{
  if(value == CRM_USB_CLOCK_SOURCE_HICK)
  {
    crm_hick_sclk_frequency_select(CRM_HICK_SCLK_48MHZ);
  }
  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->misc1_bit.hick_to_usb = value;
}






void crm_clkout_to_tmr10_enable(confirm_state new_state)
{
  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->misc2_bit.clk_to_tmr = new_state;
}
# 646 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_pll_config(crm_pll_clock_source_type clock_source, uint16_t pll_ns, uint16_t pll_ms, crm_pll_fr_type pll_fr)

{

  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->pllcfg_bit.pllrcs = clock_source;


  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->pllcfg_bit.pllns = pll_ns;
  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->pllcfg_bit.pllms = pll_ms;
  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->pllcfg_bit.pllfr = pll_fr;
}
# 667 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_sysclk_switch(crm_sclk_type value)
{
  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->cfg_bit.sclksel = value;
}
# 681 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
crm_sclk_type crm_sysclk_switch_status_get(void)
{
  return (crm_sclk_type)((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->cfg_bit.sclksts;
}







void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct)
{
  uint32_t pll_ns = 0, pll_ms = 0, pll_fr = 0, pll_clock_source = 0, pllrcsfreq = 0;
  uint32_t temp = 0, div_value = 0;
  crm_sclk_type sclk_source;

  static const uint8_t sclk_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
  static const uint8_t ahb_apb1_div_table[8] = {0, 0, 0, 0, 1, 2, 3, 4};
  static const uint8_t ahb_apb2_div_table[8] = {0, 0, 0, 0, 1, 2, 3, 4};
  static const uint8_t pll_fr_table[6] = {1, 2, 4, 8, 16, 32};


  sclk_source = crm_sysclk_switch_status_get();

  switch(sclk_source)
  {
    case CRM_SCLK_HICK:
      if(((((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->misc1_bit.hick_to_sclk) != RESET) && ((((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->misc1_bit.hickdiv) != RESET))
        clocks_struct->sclk_freq = ((uint32_t)8000000) * 6;
      else
        clocks_struct->sclk_freq = ((uint32_t)8000000);
      break;
    case CRM_SCLK_HEXT:
      clocks_struct->sclk_freq = ((uint32_t)8000000);
      break;
    case CRM_SCLK_PLL:

      pll_clock_source = ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->pllcfg_bit.pllrcs;


      pll_ns = ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->pllcfg_bit.pllns;
      pll_ms = ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->pllcfg_bit.pllms;
      pll_fr = pll_fr_table[((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->pllcfg_bit.pllfr];

      if (pll_clock_source == CRM_PLL_SOURCE_HICK)
      {

        pllrcsfreq = ((uint32_t)8000000);
      }
      else
      {

        pllrcsfreq = ((uint32_t)8000000);
      }

      clocks_struct->sclk_freq = (uint32_t)(((uint64_t)pllrcsfreq * pll_ns) / (pll_ms * pll_fr));
      break;
    default:
      clocks_struct->sclk_freq = ((uint32_t)8000000);
      break;
  }



  temp = ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->cfg_bit.ahbdiv;
  div_value = sclk_ahb_div_table[temp];

  clocks_struct->ahb_freq = clocks_struct->sclk_freq >> div_value;


  temp = ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->cfg_bit.apb1div;
  div_value = ahb_apb1_div_table[temp];

  clocks_struct->apb1_freq = clocks_struct->ahb_freq >> div_value;


  temp = ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->cfg_bit.apb2div;
  div_value = ahb_apb2_div_table[temp];

  clocks_struct->apb2_freq = clocks_struct->ahb_freq >> div_value;
}
# 774 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_clock_out1_set(crm_clkout1_select_type clkout)
{
    ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->cfg_bit.clkout1_sel = clkout;
}
# 793 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_clock_out2_set(crm_clkout2_select_type clkout)
{
  if(clkout < 0x10)
  {
    ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->cfg_bit.clkout2_sel1 = (clkout & 0x3);
  }
  else
  {
    ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->cfg_bit.clkout2_sel1 = 0x1;
    ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->misc1_bit.clkout2_sel2 = (clkout & 0xF);
  }
}
# 832 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_clkout_div_set(crm_clkout_index_type index, crm_clkout_div1_type div1, crm_clkout_div2_type div2)
{
  if(index == CRM_CLKOUT_INDEX_1)
  {
    ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->cfg_bit.clkout1div1 = div1;
    ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->misc1_bit.clkout1div2 = div2;
  }
  else
  {
    ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->cfg_bit.clkout2div1 = div1;
    ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->misc1_bit.clkout2div2 = div2;
  }
}
# 854 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_emac_output_pulse_set(crm_emac_output_pulse_type width)
{
  ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->misc2_bit.emac_pps_sel = width;
}
# 871 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state)
{
  if(TRUE == new_state)
    ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->clkint |= crm_int;
  else
    ((crm_type *) ((((uint32_t)0x40000000) + 0x20000) + 0x3800))->clkint &= ~crm_int;
}
# 905 "../Core/AT32F435CGU7/libraries/drivers/src/at32f435_437_crm.c"
error_status crm_pll_parameter_calculate(crm_pll_clock_source_type pll_rcs, uint32_t target_sclk_freq, uint16_t *ret_ms, uint16_t *ret_ns, uint16_t *ret_fr)

{
  uint32_t pll_rcs_freq = 0, ns = 0, ms = 0, fr = 0;
  uint32_t ms_min = 0, ms_max = 0, error_min = 0xFFFFFFFF;
  uint32_t result = 0, absolute_value = 0;


  target_sclk_freq = target_sclk_freq / 1000;


  if(pll_rcs == CRM_PLL_SOURCE_HICK)
    pll_rcs_freq = ((uint32_t)8000000) / 1000;
  else
    pll_rcs_freq = ((uint32_t)8000000) / 1000;


  for(ms = 1; ms <= 15; ms ++)
  {
    result = pll_rcs_freq / ms;
    if((result >= 2000U) && (result <= 16000U))
    {
      if(ms_min == 0)
        ms_min = ms;

      ms_max = ms;
    }
  }


  for(ms = ms_min; ms <= ms_max; ms ++)
  {
    for(fr = 0; fr <= 5; fr ++)
    {
      for(ns = 31; ns <= 500; ns ++)
      {
        result = (pll_rcs_freq * ns) / (ms);

        if((result < 500000U) || (result > 1000000U))
        {
          continue;
        }

        result = result / (0x1 << fr);

        if(target_sclk_freq == result)
        {
          *ret_ms = ms;
          *ret_ns = ns;
          *ret_fr = fr;

          return SUCCESS;
        }

        absolute_value = (result > target_sclk_freq) ? (result - target_sclk_freq) : (target_sclk_freq - result);
        if(absolute_value < error_min)
        {
          error_min = absolute_value;
          *ret_ms = ms;
          *ret_ns = ns;
          *ret_fr = fr;
        }
      }
    }
  }

  return ERROR;
}
